MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 355

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

The core interface supports bus pipelining, allowing the address tenure of one transaction to overlap the
data tenure of another. The extent of the pipelining depends on external arbitration and control circuitry.
Similarly, the core supports split-bus transactions for systems with multiple potential bus masters—one
device can have mastership of the address bus while another has mastership of the data bus. Allowing
multiple bus transactions to occur simultaneously increases the available bus bandwidth for other activity
and, as a result, improves performance.
The core clocking structure allows the bus to operate at integer multiples of the core cycle time.
The following sections describe the core bus support for memory operations. Note that some signals
perform different functions depending on the addressing protocol used.
7.3.7.1
The e300 core CSB is a 64-bit data bus.
With a 64-bit CSB, memory accesses allow transfer sizes of 8, 16, 24, 32, 40, 48, 56, or 64 bits in one bus
clock cycle. Data transfers occur in either single-beat transactions or four-beat burst transactions.
Single-beat transactions are caused by noncached accesses that access memory directly (that is, reads and
writes when caching is disabled, caching-inhibited accesses, and stores in write-through mode). Four-beat
burst transactions, which always transfer an entire cache block (32 bytes), are initiated when a line is read
from or written to memory.
7.3.7.2
The e300 core signals are grouped as follows:
Freescale Semiconductor
•
Interrupts/Resets—These signals include the external interrupt signal (
(
soft reset and hard reset signals. They are used to interrupt and, under various conditions, to reset
the core.
cint
), checkstop signals, performance monitor signal (pm_event_in) via the PM counters, and both
Memory Accesses
Signals
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Address Termination
Address Arbitration
Transfer Attribute
Address Transfer
Output Enable
Debug Control
Address Start
Input Enable
Clocks
Figure 7-4. Core Interface
e300 Core
1.5 V
Debug Control
Data Arbitration
Data Transfer
Data Termination
Interrupt, Checkstops
Reset
Processor Status
JTAG/Debug Interface
Test Interface
int
), critical interrupt signal
e300 Processor Core Overview
7-37