MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 791
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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MIIM registers for that eTSEC. For example, if a RTBI interface is required on eTSEC2, then the MIIM
registers starting at offset 0x2_5520 are used to configure it.
Figure 15-41
Table 15-45
15.5.3.5.7
The MIIMCOM register is written by the user.
Freescale Semiconductor
29–31
1–26
Bits
27
28
0
Offset eTSEC1:0x2_4520
Reset
Offset eTSEC1:0x2_4524
Reset
W
R
W
R
Reset Mgmt Reset management. This bit is cleared by default.
MgmtClk
Reset Mgmt
No Pre
Name
0
—
—
describes the fields of the MIIMCFG register.
describes the definition for the MIIMCFG register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0
0
MII Management Command Register (MIIMCOM)
0 Allow the MII MGMT to perform mgmt read/write cycles if requested through the host interface.
1 Reset the MII MGMT.
Reserved
Preamble suppress. This bit is cleared by default.
0 The MII MGMT performs Mgmt read/write cycles with 32 clocks of preamble.
1 The MII MGMT suppresses preamble generation and reduces the Mgmt cycle from 64 clocks to 32
Reserved
This field determines the clock frequency of the MII management clock (EC_MDC). Its default value is
111.
Note: The eTSEC system clock is derived from (CCB Clock)/2.
000 1/4 of the eTSEC system clock divided by 8
001 1/4 of the eTSEC system clock divided by 8
010 1/6 of the eTSEC system clock divided by 8
011 1/8 of the eTSEC system clock divided by 8
100 1/10 of the eTSEC system clock divided by 8
101 1/14 of the eTSEC system clock divided by 8
110 1/20 of the eTSEC system clock divided by 8
111 1/28 of the eTSEC system clock divided by 8
Figure 15-41. MII Management Configuration Register Definition
clocks. This is in accordance with IEEE 802.3/22.2.4.4.2.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Figure 15-42. MIIMCOM Register Definition
Table 15-45. MIIMCFG Field Descriptions
—
Figure 15-42
—
All zeros
Description
describes the definition for MIIMCOM.
Enhanced Three-Speed Ethernet Controllers
29
Scan Cycle
26
0
No Pre — MgmtClk
30
27
0
Access: Read/Write
Access: Read/Write
28 29
0
Read Cycle
1
31
1
15-73
31
1
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