MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 82
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Overview
The major features of this device are as follows:
1-2
•
•
•
e300c3 Power Architecture™ processor core
— High-performance, superscalar processor core with a four-stage pipeline and low interrupt
— Floating-point, dual integer units, load/store, system register, and branch processing units
— 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities
— Capable of completing two MACs every 3 cycles
— Dynamic power management
— Enhanced hardware program debug features
— Software-compatible with Freescale processor families implementing Power Architecture
— Separate PLL that is clocked by the system bus clock
— Performance monitor
IEEE 802.11i® standard, iSCSI, and IKE processing. The security engine contains one
crypto-channel, a controller, and a set of crypto execution units (EUs). The execution units are:
— Data encryption standard execution unit (DEU)
— Advanced encryption standard unit (AESU)
— Message digest execution unit (MDEU)
— One crypto-channel supporting multi-command descriptor chains
DDR SDRAM memory controller
— Programmable timing supporting both DDR1 and DDR2 SDRAM
— 16-/32-bit data interface, up to 333-MHz data rate
— 512-Mbyte addressable space
Security engine optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
latency times
technology
– DES and 3DES algorithms
– Two key (K1, K2) or three key (K1, K2, K3) for 3DES
– ECB and CBC modes for both DES and 3DES
– Implements the Rijndael symmetric-key cipher
– Key lengths of 128-, 192-, and 256-bits
– ECB, CBC, CCM, and counter (CTR) modes
– SHA with 160-, 224-, or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
– Dynamic assignment of crypto-execution units through an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
– Support for multiple outstanding bus transactions
– Scatter/gather capability
– Fetch FIFOs in the crypto-channel
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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