MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 861

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 15-142
15.6.1.6
SGMII communication using the eTSEC is accomplished through the SerDes interface. See
page 15-6
15.6.2
This section describes the operation of the eTSEC. First, the software initialization sequence is described.
Next, the software (Ethernet driver) interface for transmitting and receiving frames is reviewed. Frame
filtering and receive filing algorithm features are also discussed. The section concludes with interrupt
handling, inter-packet gap time, and loop back descriptions.
15.6.2.1
This sections describes which registers are reset due to a hard or software reset and what registers the user
must initialize prior to enabling the eTSEC.
Freescale Semiconductor
for specific signal assignments.
Gigabit Ethernet Controller Channel Operation
SGMII Interface
Initialization Sequence
describes the signals shared by all interfaces.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
GTX_CLK125
Signals
MDIO
MDC
Table 15-141. RGMII Signals Multiplexing (continued)
(TSEC n _)
Signals
Frequency [MHz] 125
RX_DV
RX_ER
COL
CRS
Sum
Voltage[V] 3.3/2.5
eTSEC Signals
Sum
Table 15-142. Shared Signals
I/O
I/O
I/O
I
I
I
I
O
I
Signals
No. of
No. of Signals
25
1
1
1
1
1
1
1
(RX_DV/RX_ERR)
(TSEC n _)
RX_CTL
Signals
Frequency [MHz] 125
RGMII Interface
Voltage[V] 2.5
Sum
Management interface clock
Management interface I/O
Reference clock
Function
Enhanced Three-Speed Ethernet Controllers
I/O
I
—
Signals
No. of
12
1
Table 15-1 on
15-143