MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 335

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

7.3.1.2
The VEA introduces the time base facility (TB) for reading. The TB is a 64-bit register pair whose contents
are incremented once every four core input clock cycles. The TB consists of two 32-bit registers—time
base upper (TBU) and time base lower (TBL). Note that the time base registers are read-only in user state.
7.3.1.3
OEA registers are supervisor-level registers that include the following.
7.3.1.3.1
The MSR is a supervisor-level register that defines the state of the core. The contents of this register are
saved when an interrupt is taken, and restored when the interrupt handling completes. A critical interrupt
interrupt is taken in the e300 core when the cint signal is asserted and MSR[CE] is set. The e300 core
implements the MSR as a 32-bit register.
Table 7-1
Freescale Semiconductor
10–12
1–4
5–9
Bits
13
14
15
16
17
0
1
1
1
1
Name
TGPR Temporary GPR remapping (implementation-specific)
POW
ILE
PR
shows the bit definitions for MSR.
EE
—
—
—
—
VEA Registers
OEA Registers
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Machine State Register (MSR)
Reserved. Full function.
Reserved. Partial function.
Reserved. Full function.
Reserved. Partial function.
Power management enable (implementation-specific)
0 Disables programmable power modes (normal operation mode)
1 Enables programmable power modes (nap, doze, or sleep mode).
This bit controls the programmable power modes only; it has no effect on dynamic power management
(DPM). MSR[POW] may be altered with an mtmsr instruction only. Also, when altering the POW bit, software
may alter only this bit in the MSR and no others. The mtmsr instruction must be followed by a
context-synchronizing instruction.
0 Normal operation
1 TGPR mode. GPR0–GPR3 are remapped to TGPR0–TGPR3 for use by TLB miss routines.
The contents of GPR0–GPR3 remain unchanged while MSR[TGPR] = 1. Attempts to use GPR4–GPR31 with
MSR[TGPR] = 1 yield undefined results. Temporarily replaces TGPR0–TGPR3 with GPR0–GPR3 for use by
TLB miss routines. The TGPR bit is set when either an instruction TLB miss, data read miss, or data write
miss interrupt is taken. The TGPR bit is cleared by an rfi instruction.
Interrupt little-endian mode. When an interrupt occurs, this bit is copied into MSR[LE] to select the endian
mode for the context established by the interrupt.
External interrupt enable
0 The processor ignores external interrupts, system management interrupts, and decrementer interrupts.
1 The processor is enabled to take an external interrupt, system management interrupt, or decrementer
Privilege level
0 The processor can execute both user- and supervisor-level instructions
1 The processor can only execute user-level instructions
interrupt.
Table 7-1. MSR Bit Descriptions
Description
e300 Processor Core Overview
7-17