MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 280
MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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System Configuration
5.8.2.5
The power management controller configuration register 2 (PMCCR2), shown in
count values used for power-up and power-down timers.
5-72
28–29
30–31
Bits
Offset 0x00B10
Reset 0
W
R
CURR_STATE
NEXT_STATE
0
Name
Power Management Controller Configuration Register 2 (PMCCR2)
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
0
Figure 5-55. Power Management Controller Configuration Register 2
0 0
3
Indicate the power state as programmed by the PCI host in PCIPMR1[Power_State]. The host will
write the Power_State bits to request that the device enter a certain low power state. The host may
also write the Power_State to request that the device return to D0 from some low power state. When
the NEXT_STATE field is different than the CURR_STATE field, an interrupt is asserted to the e300
processor through the IPIC. This field is read-only.
00 Host’s desired power state is D0
01 Host’s desired power state is D1
10 Host’s desired power state is D2
11 Host’s desired power state is D3 (either D3Hot or D3Warm)
Indicate the current power state of the device. These bits are written by the e300 just before entering
a requested low power state, or when the device has returned to the full on state (D0). Writing these
bits causes the PCIPMR1[Power_State] field to be updated informing the host that the device has
entered the requested power state.
00 Current power state is D0
01 Current power state is D1
10 Current power state is D2
11 Current power state is D3Hot (also used for D3Warm)
4
0
Table 5-70. PMCCR1 Bit Settings (continued)
0 0 0 0 0 0 0 0 1 0 0 0
RCNT
15 16
Description
—
0 0 0 0 0 0 0 0 0 0 0 0 1 0
19 20
Figure
Freescale Semiconductor
PDCNT
Access: Read/Write
5-55, contains
31
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