MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 915
MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Table 15-169
Table 15-170
Freescale Semiconductor
eTSEC Signals
GTX_CLK125
MDIO
MDC
describes the shared signals for the RGMII interface.
describes the register initializations required to configure the eTSEC in RGMII mode.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Sum
Table 15-168. RGMII Interface Mode Signal Configuration (continued)
Signals
RX_ER
CRS
COL
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
I/O
I/O
Sum
Table 15-170. RGMII Mode Register Initialization Steps
O
I
(This example has RGMII 10Mbps mode, Statistics Enable = 1)
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
eTSEC Signals
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
Signals
No. of
1
1
1
Table 15-169. Shared RGMII Signals
I/O
I
I
I
to 02608C:876543, for example.
to 02608C:876543, for example.
Initialize MAC Station Address,
Initialize MAC Station Address,
(I/F Mode = 2, Full Duplex = 1)
GTX_CLK125
GMII Signals
Signals
No. of
Initialize MACCFG2,
MDIO
MDC
Initialize ECNTRL,
17
Clear Soft_Reset,
1
1
1
Set Soft_Reset,
Sum
I/O
I/O
O
Signals
I
Frequency [MHz] 125
Signals
Sum
No. of
RGMII Interface
Voltage [V] 2.5
1
1
1
not used
not used
not used
Enhanced Three-Speed Ethernet Controllers
I/O
Management interface clock
Management interface I/O
Reference clock
Signals
No. of
Function
12
15-197
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