MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 474
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Enhanced Local Bus Controller
Table 10-16
10-26
10–11
13–29
Bits
3–4
6–7
12
30
31
0
1
2
5
8
9
ATMW Atomic error write
Name
ATMR Atomic error read
UCC
FCT
PAR
BM
WP
CS
CC
—
—
—
—
describes LTESR fields.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Bus monitor time-out
0 No local bus monitor time-out occurred.
1 Local bus monitor time-out occurred. No data beat was acknowledged on the bus within
FCM command time-out
0 No FCM command time-out occurred.
1 A CW0, CW1, CW2, or CW3 command issued to FCM timed-out with respect to the timer configured by
ECC error for FCM mode
0 No local bus ECC error
1 Uncorrectable ECC error (FCM). LTEATR[PB] indicates the block that caused the error and LTEATR[BNK]
Reserved
Write protect error
0 No write protect error occurred.
1 A write was attempted to a local bus memory region that was defined as read-only in the memory
Reserved
0 No atomic write error occurred.
1 The subsequent write (WARA) to a memory bank did not occur within 256 bus clock cycles.
0 No atomic read error occurred.
1 The subsequent read (RAWA) to a memory bank did not occur within 256 bus clock cycles.
Reserved
Chip select error
0 No chip select error occurred.
1 A transaction was sent to the eLBC that did not hit any memory bank.
Reserved
UPM Run pattern (MxMR[OP]=11) command completion event
0 No UPM Run pattern operation in progress, or operation pending.
1 UPM Run pattern operation has completed, allowing software to continue processing of results.
FCM command completion event
0 No FCM operation in progress, or operation pending.
1 FCM operation has completed, allowing software to continue processing of results.
LBCR[BMT] x LBCR[BMTPS] bus clock cycles from the start of a transaction.
FMR[CWTO].
indicates which memory controller bank was accessed.
controller. Usually, in this case, a bus monitor time-out will occur (as the cycle is not automatically
terminated).
Table 10-16. LTESR Field Descriptions
Description
Freescale Semiconductor
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