MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 49
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Freescale Semiconductor
Receive Queue Filer Table Address Register Definition .................................................... 15-56
Receive Queue Filer Table Control Register Definition ..................................................... 15-56
Receive Queue Filer Table Property IDs 0, 2–15 Register Definition................................ 15-57
Receive Queue Filer Table Property ID1 Register Definition ............................................ 15-58
MRBLR Register Definition ............................................................................................... 15-61
RBDBPH Register Definition............................................................................................. 15-62
RBPTR0–RBPTR7 Register Definition .............................................................................. 15-62
RBASE Register Definition ................................................................................................ 15-63
TMR_RXTS_H/L Register Definition................................................................................ 15-64
MACCFG1 Register Definition .......................................................................................... 15-67
MACCFG2 Register Definition .......................................................................................... 15-68
IPGIFG Register Definition ................................................................................................ 15-70
Half-Duplex Register Definition......................................................................................... 15-71
Maximum Frame Length Register Definition..................................................................... 15-72
MII Management Configuration Register Definition ......................................................... 15-73
MIIMCOM Register Definition .......................................................................................... 15-73
MIIMADD Register Definition .......................................................................................... 15-74
MII Mgmt Control Register Definition............................................................................... 15-75
MIIMSTAT Register Definition .......................................................................................... 15-75
MII Mgmt Indicator Register Definition ............................................................................ 15-76
Interface Status Register Definition .................................................................................... 15-76
MAC Station Address Part 1 Register Definition ............................................................... 15-77
MAC Station Address Part 2 Register Definition ............................................................... 15-78
MAC Exact Match Address n Part 1 Register Definition ................................................... 15-78
MAC Exact Match Address x Part 2 Register Definition ................................................... 15-79
Transmit and Receive 64-Byte Frame Register Definition ................................................. 15-80
Transmit and Receive 65- to 127-Byte Frame Register Definition .................................... 15-80
Transmit and Received 128- to 255-Byte Frame Register Definition ................................ 15-81
Transmit and Received 256- to 511-Byte Frame Register Definition................................. 15-81
Transmit and Received 512- to 1023-Byte Frame Register Definition .............................. 15-82
Transmit and Received 1024- to 1518-Byte Frame Register Definition ............................ 15-82
Transmit and Received 1519- to 1522-Byte VLAN Frame Register Definition ................ 15-83
Receive Byte Counter Register Definition.......................................................................... 15-83
Receive Packet Counter Register Definition ...................................................................... 15-83
Receive FCS Error Counter Register Definition................................................................. 15-84
Receive Multicast Packet Counter Register Definition ...................................................... 15-84
Receive Broadcast Packet Counter Register Definition ..................................................... 15-85
Receive Control Frame Packet Counter Register Definition .............................................. 15-85
Receive Pause Frame Packet Counter Register Definition ................................................. 15-86
Receive Unknown OPCode Packet Counter Register Definition ....................................... 15-86
Receive Alignment Error Counter Register Definition....................................................... 15-87
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figures
Title
Number
Page
xlix
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