MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 216
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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System Configuration
5.2.4.3
The LBC local access window n base address registers (LBLAWBAR0–LBLAWBAR3) are shown in
Figure
Table 5-7
5.2.4.3.1
The core may also use a local bus peripheral device to fetch its boot vector. For this purpose, the
LBLAWBAR0[BASE_ADDR] reset value is set according to the value set in the reset configuration word
high BMS field.
Table 5-8
5-8
1. The LBLAWBAR0[BASE_ADDR] reset value depends on the reset configuration word high values. See
20–31
0–19
‘
‘
Bits
“LBLAWBAR0[BASE_ADDR] Reset Value,”
Offset 0x20, 0x28, 0x30, 0x38
Reset
Figure 5-4. LBC Local Access Window n Base Address Registers (LBLAWBAR0–LBLAWBAR3)
W
R
5-4.
BASE_ADDR Identifies the 20 most-significant address bits of the base of local access window n . The specified
0
defines the bit fields of LBLAWBAR0–LBLAWBAR3.
defines the reset value of LBLAWBAR0[BASE_ADDR].
Name
—
LBC Local Access Window n Base Address Registers
(LBLAWBAR0–LBLAWBAR3)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
LBLAWBAR0[BASE_ADDR] Reset Value
base address should be aligned to the window size, as defined by LBLAWARn[SIZE].
Reserved. Write has no effect, read returns 0.
Table 5-8. LBLAWBAR0[BASE_ADDR] Reset Value
Table 5-7. LBLAWBAR0–LBLAWBAR3 Bit Settings
RCWHR[BMS]
BASE_ADDR
0
1
for a detailed description.
BASE_ADDR Reset Value
All zeros
Description
0xFF800
0x00000
19 20
Freescale Semiconductor
—
Access: Read/Write
Section 5.2.4.3.1,
31
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