MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 305
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Table 6-2
Freescale Semiconductor
10–11
13–15
17–19
21–23
24–25
Bits
0–6
8–9
12
16
20
7
PCI_RPTCNT PCI repeat count.
PIPE_DEP
describes ACR fields.
COREDIS
RPTCNT
Name
—
—
—
—
—
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved, write should preserve reset value.
Core disable. Specifies whether CPU is disabled. When CPU is disabled, it cannot be granted on the
bus by the arbiter. After reset, this bit receives it’s value from the reset configuration bit of COREDIS
and can be configured by software. Also, if boot source is boot sequencer, COREDIS must be set to
1 at reset and the last transaction of the boot sequencer must set COREDIS to 0, if CPU enable is
needed.
0 CPU enabled.
1 CPU disabled.
Write reserved, read = 0
Reserved. Write should preserve reset value.The reset value is a function of the core PLL
configuration, which is part of the reset configuration word. When the core is set to operate at 1:1 or
3:2 bus clock, these bits are set to ‘01’ during reset; otherwise, they are set to ‘00’.
Reserved, write should preserve reset value.
Pipeline depth (number of outstanding transactions).
000 Pipeline depth 1 (1 outstanding transaction)
001 Pipeline depth 2 (2 outstanding transactions)
010 Pipeline depth 3 (3 outstanding transactions)
011 Pipeline depth 4 (4 outstanding transactions)
1xx Reserved
Reserved, write should preserve reset value.
Specifies the maximum number of consecutive transactions, that PCI master can perform, using
REPEAT request mode.
000 One consecutive transaction (REPEAT request mode disable)
001 Two consecutive transactions
010 Three consecutive transactions
011 Four consecutive transactions
100 Five consecutive transactions
101 Six consecutive transactions
110 Seven consecutive transactions
111 Eight consecutive transactions
Reserved, write should preserve reset value.
Repeat count. Specifies the maximum number of consecutive transactions, that any master (except
PCI) can perform, using REPEAT request mode.
000 1 consecutive transactions (REPEAT request mode disable)
001 2 consecutive transactions
010 3 consecutive transactions
011 4 consecutive transactions
100 5 consecutive transactions
101 6 consecutive transactions
110 7 consecutive transactions
111 8 consecutive transactions
Note: It is recommended not to program this field for more than four consecutive transactions.
Reserved, write should preserve reset value.
Table 6-2. ACR Field Descriptions
Description
Arbiter and Bus Monitor
6-3
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