MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 75

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about the architecture.
General Information
The following documentation, published by Morgan-Kaufmann Publishers, 340 Pine Street, Sixth Floor,
San Francisco, CA, provides useful information about the PowerPC architecture and computer architecture
in general:
Freescale Semiconductor
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Chapter 16, “Universal Serial Bus Interface,”
The USB DR module is a USB 2.0-compliant serial interface engine for implementing a USB
interface. The registers and data structures are based on the Enhanced Host Controller Interface
Specification for Universal Serial Bus (EHCI) from Intel Corporation. The USB DR module can
act as a host, as a device, or as an on-the-go (OTG) negotiable host/device on the USB bus. The
USB DR module allows either an internal PHY to be connected to the UTMI interface or an
external PHY to be connected to the ULPI interface.
Chapter 17, “I
These synchronous, serial, bidirectional, multiple-master buses allow two-wire connection of
devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCDs.
The MPC8313E powers up in boot sequencer mode, which allows the I
configuration registers.
Chapter 18, “DUART,”
(UARTs) which feature a PC16552D-compatible programming model. These independent UARTs
are provided specifically to support system debugging.
Chapter 19, “Serial Peripheral Interface,”
(SPI) that allows the exchange of data between MPC83xx family devices. The SPI can also be used
to communicate with peripheral devices such as EEPROMs, real-time clocks, A/D converters, and
ISDN devices.
Chapter 20, “JTAG/Testing Support,”
MPC8349E to facilitate boundary-scan testing. The JTAG interface complies to the IEEE 1149.1™
boundary-scan specification.
Chapter 21, “General Purpose I/O (GPIO),”
the MPC8313E device, including a definition of the external signals and functions they serve.
Additionally, interrupt capabilities, pin description, and register settings are described.
This reference manual also includes a revision history, glossary, and an index.
The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition,
by International Business Machines, Inc.
Computer Architecture: A Quantitative Approach, Third Edition, by John L. Hennessy and
David A. Patterson.
Computer Organization and Design: The Hardware/Software Interface, Second Edition, by
David A. Patterson and John L. Hennessy.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
C Interface,”
describes the (dual) universal asynchronous receiver/transmitters
describes the inter-IC (IIC or I
describes the joint test action group (JTAG) interface of the
describes the MPC8313E serial peripheral interface
describes the general purpose I/O (GPIO) module in
describes the universal serial bus (USB) interface.
2
C) bus controllers of the MPC8313E.
2
C controllers to initialize
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