MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 897
MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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15.6.6.2
The 1588 timer module can be partitioned into four different sub-modules as shown in
15.6.6.3
Every incoming packet’s 8-byte timestamp is inserted into the packet data buffer as padding alignment
bytes. Timestamp insertion into the data buffer requires RCTRL[PAL] to be set to a value greater than or
equal to 8 and the control bit RCTRL[TS] bit to be set.
15.6.6.3.1
The required timestamp point, as specified in the IEEE 1588 Specification Sep-2004 (IEC 61588 First
Edition), is shown in Figure 15-140. From this, it is clear that the end of the SFD is the critical point in the
MII data stream.
Freescale Semiconductor
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•
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Recognition of incoming PTP packet through filer rule match
Phase aligned adjustable (divide by N) clock output
Supports all Ethernet modes supported by the eTSEC, including full- and half-duplex modes
Supports both master and slave modes
Supports timestamp of nano-second resolution
Timer Logic Overview
Timestamp Insertion on the Received Packets
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Timestamp Point
1588 Timer
TMRCK
Clock
Figure 15-139. 1588 Timer Design Partition
TMRMAC
SFD Detection
TMRREG
Rx & Tx
Register Array
Timestamp
SEL
Rx Pins
Enhanced Three-Speed Ethernet Controllers
Ethernet MAC
eTSEC
Tx Pins
Figure
15-139.
15-179
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