DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 121

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

DS21455/DS21458 Quad T1/E1/J1 Transceivers
20.4 Minimum-Delay Mode
When minimum delay mode is enabled the elastic stores will be forced to a maximum depth of 32 bits
instead of the normal two-frame depth. ESCR.5 and ESCR.1 enable the transmit and receive elastic store
minimum-delay modes. This feature is useful primarily in applications that interface T1 to a 2.048MHz
bus without adding the latency that would be associated with using the elastic store in full buffer mode.
Certain restrictions apply when minimum delay mode is used. Minimum-delay mode can only be
used when the elastic store’s system clock is locked to its network clock (e.g., RCLK locked to
RSYSCLK for the receive side and TCLK locked to TSYSCLK for the transmit side). RSYNC must be
configured as an output. In E1 operation TSYNC must be configured as an input when transmit
minimum delay mode is enabled. In T1 operation TSYNC can be configured as an input or output when
transmit minimum delay mode is enabled. In a typical application RSYSCLK and TSYSCLK are locked
to RCLK, and RSYNC (frame output mode) is connected to TSSYNC (frame input mode). All of the slip
contention logic in the framer is disabled (since slips cannot occur). On power-up, after the RSYSCLK
and TSYSCLK signals have locked to their respective network clock signals, the elastic store reset bits
(ESCR.2 and ESCR.6) should be toggled from a zero to a one to ensure proper operation.
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