DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 253
DS21458LDK
Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS21458LDK.pdf
(269 pages)
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38. AC TIMING PARAMETERS AND DIAGRAMS
Capacitive test loads are 40pF for bus signals, 20pF for all others.
38.1 Multiplexed Bus AC Characteristics
AC CHARACTERISTICS–MULTIPLEXED PARALLEL PORT (MUX = 1)
(V
V
Cycle Time
Pulse Width, DS Low or RD High
Pulse Width, DS High or RD Low
Input Rise/Fall Times
R/W Hold Time
R/W Setup Time Before DS High
CS Setup Time Before DS, WR, or
RD Active
CS Hold Time
Read Data Hold Time
Write Data Hold Time
Muxed Address Valid to AS or ALE
Fall
Muxed Address Hold Time
Delay Time DS, WR, or RD to AS
or ALE Rise
Pulse Width AS or ALE High
Delay Time, AS or ALE to DS, WR,
or RD
Output Data Delay Time from DS or
RD
Data Setup Time
DD
DD
= 3.3V 5%, T
= 3.3V 5%, T
PARAMETER
A
A
= -40C to +85C for DS21455N/DS21458N.) (See
= 0°C to +70°C for DS21455/DS21458;
SYMBOL
PW
PW
PW
t
t
t
t
t
t
t
t
t
t
t
t
ASED
R
RWH
DHW
RWS
t
DHR
DDR
DSW
CYC
t
AHL
ASD
ASL
CH
CS
, t
ASH
EH
EL
F
253 of 269
MIN
200
100
100
10
50
20
10
15
10
20
30
10
50
0
5
DS21455/DS21458 Quad T1/E1/J1 Transceivers
TYP
Figure 38-1
MAX
20
50
80
UNITS
to
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
38-3.)
NOTES
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