DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 260
![no-image](/images/no-image-200.jpg)
DS21458LDK
Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS21458LDK.pdf
(269 pages)
- Current page: 260 of 269
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AC CHARACTERISTICS–RECEIVE SIDE (continued)
(V
V
NOTES:
1) Jitter attenuator enabled in the receive path.
2) Jitter attenuator disabled or enabled in the transmit path.
3) RSYSCLK = 1.544MHz.
4) RSYSCLK = 2.048MHz.
5) RSYSCLK = 4.096MHz.
6) RSYSCLK = 8.192MHz.
7) RSYSCLK = 16.384MHz.
Figure 38-8. Receive Side Timing, Elastic Store Disabled (T1 Mode)
DD
DD
RSER / RDATA / RSIG
NOTES:
1) RSYNC is in the output mode.
2) Shown is RLINK/RLCLK in the ESF framing mode.
3) No relationship between RCHCLK and RCHBLK and other signals is implied.
= 3.3V 5%, T
RFSYNC / RMSYNC
= 3.3V 5%, T
RCHCLK
RCHBLK
RSYNC
RLCLK
RLINK
RCLK
A
A
= -40C to +85C for DS21455N/DS21458N.) (See
= 0C to +70C for DS21455/DS21458;
1
2
t D1
t D1
t D2
t D2
t D2
t D2
t
D2
260 of 269
F Bit
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 38-8
to
Figure
38-12.)
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