DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 188

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 3/Repetitive Pattern Length Bit 3 (RPL0 to RPL3). RPL0 is the LSB and RPL3 is the MSB of a nibble that
describes the how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are ignored if the receive
BERT is programmed for a pseudorandom pattern. To create repetitive patterns less than 17 bits in length, the user must set the
length to an integer number of the desired length that is less than or equal to 32. For example, to create a 6-bit pattern, the user
can set the length to 18 (0001) or to 24 (0111) or to 30 (1101).
Bit 4/Single Bit Error Insert (SBE). A low-to-high transition will create a single bit error. Must be cleared and set again for a
subsequent bit error to be inserted.
Bits 5 to 7/Error Insert Bits 0 to 2 (EIB0 to EIB2). Will automatically insert bit errors at the prescribed rate into the
generated data pattern. Can be used for verifying error detection features.
Length
EIB2
(Bits)
0
0
0
0
1
1
1
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
EIB1
RPL3
0
0
1
1
0
0
1
1
EIB2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
7
0
EIB0
0
1
0
1
0
1
0
1
RPL2
EIB1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BC2
BERT Control Register 2
E1h
6
0
No errors automatically inserted
10E-1
10E-2
10E-3
10E-4
10E-5
10E-6
10E-7
ERROR RATE INSERTED
RPL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
EIB0
5
0
RPL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SBE
4
0
188 of 269
RPL3
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
RPL2
2
0
RPL1
1
0
RPL0
0
0