DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 189

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/BERT Enable (BERTEN).
Bit 1/BERT Direction (BERTDIR).
Bit 2/Unused, must be set to zero for proper operation.
Bit 3/Transmit Framed/Unframed Select (TFUS). For T1 mode only.
Bit 4/Transmit Byte Align Toggle (TBAT). A zero-to-one transition will force the BERT to byte align its pattern with the
transmit formatter. This bit must be transitioned in order to byte-align the Daly Pattern.
Bit 5/Unused, must be set to zero for proper operation.
Bit 6/Receive Framed/Unframed Select (RFUS). For T1 mode only.
Bit 7/Unused, must be set to zero for proper operation.
0 = BERT disabled
1 = BERT enabled
0 = network: BERT transmits toward the network (TTIP and TRING) and receives from the network (RTIP and
RRING). The BERT pattern can be looped back to the receiver internally by using the Framer Loopback function.
1 = system: BERT transmits toward the system backplane (RSER) and receives from the system backplane (TSER)
0 = BERT will not source data into the F-bit position (framed)
1 = BERT will source data into the F-bit position (unframed)
0 = BERT will not sample data from the F-bit position (framed)
1 = BERT will sample data from the F-bit position (unframed)
—
7
0
RFUS
BIC
BERT Interface Control Register
EAh
6
0
—
5
0
TBAT
4
0
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TFUS
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
—
2
0
BERTDIR
1
0
BERTEN
0
0