DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 8

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

DS21455/DS21458 Quad T1/E1/J1 Transceivers
LIST OF TABLES
Table 5-1. DS21455 Pin Description ......................................................................................................................... 29
Table 5-2. DS21458 Pin Description ......................................................................................................................... 34
Table 6-1. Register Map Sorted By Address ............................................................................................................. 41
Table 10-1. T1 Alarm Criteria .................................................................................................................................... 63
Table 11-1. E1 Sync/Resync Criteria......................................................................................................................... 65
Table 11-2. Auto E-Bit Conditions ............................................................................................................................. 68
Table 11-3. E1 Alarm Criteria .................................................................................................................................... 70
Table 14-1. LIUC Control........................................................................................................................................... 82
Table 15-1. T1 Line Code Violation Counting Options .............................................................................................. 86
Table 15-2. E1 Line Code Violation Counting Options .............................................................................................. 86
Table 15-3. T1 Path Code Violation Counting Arrangements ................................................................................... 88
Table 15-4. T1 Frames Out of Sync Counting Arrangements ................................................................................... 89
Table 17-1. Time Slot Numbering Schemes............................................................................................................ 101
Table 18-1. Idle Code Array Address Mapping ....................................................................................................... 108
Table 20-1. Elastic Store Delay After Initialization................................................................................................... 120
Table 24-1. HDLC Controller Registers ................................................................................................................... 142
Table 25-1. TPD Control.......................................................................................................................................... 164
Table 25-2. E1 Mode With Automatic Gain Control Mode Enabled (TLBC.6 = 0) .................................................. 165
Table 25-3. E1 Mode With Automatic Gain Control Mode Disabled (TLBC.6 = 1).................................................. 165
Table 25-4. T1 Mode With Automatic Gain Control Mode Enabled (TLBC.6 = 0)................................................... 165
Table 25-5. T1 Mode With Automatic Gain Control Mode Disabled (TLBC.6 = 1).................................................. 165
Table 25-6. Component List (Software-Selected Termination, Metallic Protection)................................................ 173
Table 25-7. Component List (Software-Selected Termination, Longitudinal Protection) ........................................ 174
Table 25-8. Transformer Specifications................................................................................................................... 175
Table 28-1. Transmit Error Insertion Setup Sequence ............................................................................................ 195
Table 28-2. Error Insertion Examples ...................................................................................................................... 197
Table 35-1. Instruction Codes for IEEE 1149.1 Architecture................................................................................... 220
Table 35-2. ID Code Structure................................................................................................................................. 221
Table 35-3. Device ID Codes................................................................................................................................... 221
Table 35-4. Boundary Scan Control Bits ................................................................................................................. 223
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