DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 232

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DS21458LDK

Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
Figure 36-5. Receive Side 2.048MHz Boundary Timing (With Elastic Store
Enabled)
NOTES:
1) RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to one.
2) RSYNC is in the output mode (IOCR1.4 = 0).
3) RSYNC is in the input mode (IOCR1.4 = 1).
4) RCHBLK is forced to one in the same channels as RSER (Note 1).
5) The F-bit position is passed through the receive-side elastic store.
RCHBLK
RSYSCLK
RMSYNC
RCHCLK
RSYNC
RSYNC
RSER
RSIG
3
2
4
1
CHANNEL 31
A
CHANNEL 31
B
C/A D/B
LSB MSB
232 of 269
CHANNEL 32
A
DS21455/DS21458 Quad T1/E1/J1 Transceivers
CHANNEL 32
B
C/A D/B
LSB
CHANNEL 1
CHANNEL 1

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