DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 238
DS21458LDK
Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS21458LDK.pdf
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36.2 E1 Mode
Figure 36-11. Receive Side Timing
NOTES:
1) RSYNC in frame mode (IOCR1.5 = 0).
2) RSYNC in multiframe mode (IOCR1.5 = 1).
3) RLCLK is programmed to output just the Sa bits.
4) RLINK will always output all five Sa bits as well as the rest of the receive data stream.
5) This diagram assumes the CAS MF begins in the RAF frame.
RFSYNC
RSYNC
RSYNC
RLCLK
FRAME#
RLINK
2
4
3
1
1
2
3
4
5
6
7
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
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