DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 247
DS21458LDK
Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS21458LDK.pdf
(269 pages)
DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-20. Transmit Side Boundary Timing, TSYSCLK = 1.544MHz
(With Elastic Store Enabled)
TSYSCLK
CHANNEL 23
CHANNEL 24
CHANNEL 1
1
LSB MSB
LSB
F MSB
TSER
TSSYNC
TCHCLK
2
TCHBLK
NOTES:
1) The F-bit position in the TSER data is ignored.
2) TCHBLK is programmed to block channel 24.
247 of 269
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