DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 190

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/BERT in Synchronization Condition (BSYNC). Will be set when the incoming pattern matches for 32 consecutive bit
positions. Refer to BSYNC in INFO2 register for a real-time version of this bit.
Bit 1/BERT Receive Loss Of Synchronization Condition (BRLOS). A latched bit that is set whenever the receive BERT
begins searching for a pattern. The BERT will lose sync after receiving six errored bits out of 63 bits. Synchronization is lost
when six errors are received in 63 bits. Once synchronization is achieved, this bit will remain set until read.
Bit 2/BERT Receive All Zeros Condition (BRA0). A latched bit that is set when 32 consecutive zeros are received. Allowed
to be cleared once a one is received.
Bit 3/BERT Receive All Ones Condition (BRA1). A latched bit that is set when 32 consecutive ones are received. Allowed
to be cleared once a zero is received.
Bit 4/BERT Error Counter Overflow (BECO) Event (BECO). A latched bit that is set when the 24-bit BERT error counter
(BEC) overflows. Cleared when read and will not be set again until another overflow occurs.
Bit 5/BERT Bit Counter Overflow Event (BBCO). A latched bit that is set when the 32-bit BERT bit counter (BBC)
overflows. Cleared when read and will not be set again until another overflow occurs.
Bit 6/BERT Bit Error Detected (BED) Event (BBED). A latched bit that is set when a bit error is detected. The receive
BERT must be in synchronization for it detect bit errors. Cleared when read.
—
7
0
BBED
SR9
Status Register 9
26h
6
0
BBCO
5
0
BEC0
4
0
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BRA1
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
BRA0
2
0
BRLOS
1
0
BSYNC
0
0