DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 220

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

35.1 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.
When the TAP controller enters the shift-IR state, the instruction shift register will be connected between
JTDI and JTDO. While in the shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data
one stage towards the serial output at JTDO. A rising edge on JTCLK in the exit1-IR state or the exit2-IR
state with JTMS HIGH will move the controller to the update-IR state. The falling edge of that same
JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions
supported by the DS21455/DS21458 and their respective operational binary codes are shown in
Table
Table 35-1. Instruction Codes for IEEE 1149.1 Architecture
SAMPLE/PRELOAD
35-1.
INSTRUCTION
BYPASS
IDCODE
EXTEST
CLAMP
HIGH-Z
SELECTED REGISTER
Device Identification
Boundary Scan
Boundary Scan
Bypass
Bypass
Bypass
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
INSTRUCTION CODES
010
111
000
011
100
001