MAX5980GTJ+T Maxim Integrated, MAX5980GTJ+T Datasheet - Page 12

• Manufacturer Part Number: MAX5980GTJ+T
• Description: Power Switch ICs - POE / LAN 0-16V Hot-Swap Controller
• Manufacturer: Maxim Integrated

Specifications of MAX5980GTJ+T

• Rohs: yes
• Number Of Switches: Quad
• Off Time (max): 0.1 ms
• Operating Supply Voltage: 32 V to 60 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 2758.6 mW
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 5 mA

Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
12
5, 6, 7, 8
PIN
10
1
2
3
4
9
SDAOUT
A0, A1,
NAME
SDAIN
A2, A3
DGND
SVEE2
SCL
EN
3-Wire Serial Interface Input Clock Line. Referenced to DGND. Connect to DGND if the I
not used.
Serial Interface Data Line Output. Referenced to DGND. Connect to DGND if the I
used.
Serial Interface Data Line Input. Referenced to DGND. Connect to DGND if the I
used.
EN Input. Referenced to DGND. Connect EN to V
normal operation. See the Hardware Power-Down section for details.
Slave Address Bits 0, 1, 2, 3 (Respectively). Referenced to DGND. The slave address bits are used
to form bits 3, 2, 1, and 0 of the device address (0:1:0:A3:A2:A1:A0; see Table 3). The slave address
bits are internally pulled up to V
(0101111). Connect one or more to DGND to change the device address. The slave address is
latched-in after the device is powered up or after a reset condition.
Digital Low-Side Supply Input. Connect to V
Port 3/4 Current-Sense Negative Terminal Input. Use Kelvin-sensing technique in PCB layout for best
accuracy current sensing.
TOP VIEW
MIDSPAN
*CONNECT TO V
EN_CL5
GATE1
SVEE1
AUTO
OUT1
N.C.
INT
25
26
27
28
29
30
31
32
EE
24
1
+
23
2
22
3
DD
MAX5980
. Leave them unconnected to use the default device address
21
TQFN
4
20
5
EE
19
6
FUNCTION
externally.
*EP
18
7
DD
externally through a pullup resistor to enable
17
8
16
15
14
13
12
11
10
9
GATE4
SENSE4
AGND
N.C.
V
V
SVEE2
DGND
DD
EE
Pin Configuration
Pin Description
2
C interface is not
2
C interface is not
2
C interface is