MAX5980GTJ+T Maxim Integrated, MAX5980GTJ+T Datasheet - Page 46

• Manufacturer Part Number: MAX5980GTJ+T
• Description: Power Switch ICs - POE / LAN 0-16V Hot-Swap Controller
• Manufacturer: Maxim Integrated

Specifications of MAX5980GTJ+T

• Rohs: yes
• Number Of Switches: Quad
• Off Time (max): 0.1 ms
• Operating Supply Voltage: 32 V to 60 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 2758.6 mW
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 5 mA

Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
Table 41. Port Current-Limit Register
The Port Current-Limit registers (Table 41) are used to set
the current-limit SENSE_ voltage threshold for the corre-
sponding port. On a power-up or after a reset condition,
these registers are set to a default value of 80h. Bit 7 is
hardwired to 1, while bits 5 to 0 are hardwired to 0. ILIM_
(bit 6) is set to 0 for a Class 0–3 PD, and to 1 for a Class
4 or 5 PD. The state of ILIM and the classification result
(in the case of Class 5) determine the current limit (see
the Electrical Characteristics table, V
Table 40. Port Overcurrent Register
Table 42. Port High-Power Status Register
46
PONG_PD_
CUT_RNG_
ADDRESS = 49h, 4Eh, 53h, 58h
FET_BAD_
ADDRESS = 47h, 4Ch, 51h, 56h
ADDRESS = 48h, 4Dh, 52h, 57h
ICUT_[5:0]
SYMBOL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SYMBOL
SYMBOL
RDIS_
ILIM_
1
0
0
0
0
0
0
BIT NO.
BIT NO.
BIT NO.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
(R48h, R4Dh, R52h, and R57h)
Port Current-Limit Register
TYPE
TYPE
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
—
—
—
SU_LIM
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Set to 1 if a FET failure is detected on the corresponding port
Set to 1 when a 2-event classification has occurred
Sets the current-sense scale on the corresponding port; always set to 1
ICUT is doubled when set to 0
Sets the overcurrent SENSE_ voltage threshold (V
Hardwired to 1
Current-limit setting for the corresponding port
Hardwired to 0
for details).
The Port High-Power Status registers (Table 42) are
used to external FET failures and successful 2-event
classification results. On a power-up or after a reset
condition, these registers are set to a default value of
00h. FET_BAD_ is set to 1 if the port is powered, there
is no current-limit condition, and V
PONG_PD_ is set to 1 every time a successful 2-event
classification occurs on the corresponding port.
DESCRIPTION
DESCRIPTION
DESCRIPTION
Port High-Power Status Register
CUT
(R49h, R4Eh, R53h, and R58h)
) for the corresponding port
OUT_
- V
EE
> 2V.