MAX5980GTJ+T Maxim Integrated, MAX5980GTJ+T Datasheet - Page 21

• Manufacturer Part Number: MAX5980GTJ+T
• Description: Power Switch ICs - POE / LAN 0-16V Hot-Swap Controller
• Manufacturer: Maxim Integrated

Specifications of MAX5980GTJ+T

• Rohs: yes
• Number Of Switches: Quad
• Off Time (max): 0.1 ms
• Operating Supply Voltage: 32 V to 60 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 2758.6 mW
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 5 mA

Figure 4. V
The device contains undervoltage and overvoltage pro-
tection features, and the flag bits can be found in the
Supply Event register (R0Ah and R0Bh, Table 12) and
the Watchdog register (R42h, Table 36). An internal V
undervoltage lockout circuit keeps the MOSFET off and
the device in reset until V
more than 3ms. An internal V
down the ports when V
digital supply also contains an undervoltage lockout that
triggers when V
The DC disconnect monitoring settings are found in the
Disconnect Enable register (R13h, Table 21). To enable
DC disconnect, set either the ACD_EN_ or DCD_EN_ bit
for the corresponding port to 1. To disable the DC discon-
nect monitoring, both the ACD_EN_ and DCD_EN_ bit for
that port must be set to 0. When enabled, if V
(the voltage across R
disconnect threshold, V
device turns off power and asserts the DIS_ bit for the
corresponding port (R06h[7:4] and R07h[7:4], Table 10).
The device has an internally regulated, 3.3V digital sup-
ply that powers the internal logic circuitry. V
undervoltage lockout (V
voltage condition on V
the ports shut off. When V
reset condition clears, the VDD_UVLO bit in the Supply
Event registers is set to 1 (R0Ah[5] and R0Bh[5], Table
12). The digital address inputs, AUTO, and MIDSPAN
are internally pulled up to V
referenced to DGND. V
up to 10mA for external circuitry. For internal regulator
stability, connect a 1.8kI resistor in parallel with a 33nF
capacitor at the V
Undervoltage and Overvoltage Protection
DD
External Power Sourcing
DD
DD
- V
EE
SENSE_
DD
DC Disconnect Monitoring
output (Figure 4). If an external
AGND
DD_UVLO
DD
DCTH
P 2V.
AGND
keeps the device in reset and
Quad, IEEE 802.3at/af PSE Controller
DD
can also be used to source
DD
EE
) falls below the DC load
, for more than t
- V
, and all digital inputs are
MAX5980
- V
overvoltage circuit shuts
has recovered and the
EE
V
) of 2V, and an under-
EE
DD
exceeds 62.5V. The
DGND
exceeds 28.5V for
V
Power Supply
DD
DD
DISC
RSENSE_
has an
1.8kI
, the
EE
for Power-over-Ethernet
I
EXTERNAL
load is to be shared among multiple MAX5980 devices,
isolate the external supply bus with a series resistor (50I
for 3 devices, 75I for 4 devices), and place a single 1FF
capacitor on the bus.
The EN digital input is referenced to DGND and is used
for hardware level control of device power management.
During normal operation, EN should be externally pulled
directly up to V
the Typical Operating Circuit).
To initiate a hardware reset and port power-down, pull
EN to DGND for at least 100Fs. While EN is held low, the
device remains in reset and the ports remain securely
powered down. Normal device operation resumes once
EN is pulled up to the V
If the device's die temperature reaches +140NC (typ),
an overtemperature fault is generated and the device
shuts down. The die temperature must cool down below
+120NC (typ) to remove the overtemperature fault con-
dition. After a thermal shutdown condition clears, the
device is reset and the TSD event bit is set to a logical 1
(R0Ah[7]/R0Bh[7], Table 12).
The Watchdog register (R42h, Table 36) is used to
monitor device status, and to enable and monitor the
watchdog functionality. On a power-up or after a reset
condition, this register is set to a default value of 16h.
WD_DIS[3:0] is set by default to 1011, disabling the
watchdog timeout. Set WD_DIS[3:0] to any other value
to enable the watchdog. The watchdog monitors the
SCL line for activity. If there are no transitions for 2.5s
(typ), the WD_STAT bit is set to 1 and all ports are pow-
ered down (using the individual port reset protocol).
WD_STAT must be reset before any port can be reenabled.
33nF
P 10mA
R
ISOLATION
DD
, the 3.3V internal regulator output (see
1µF
EXTERNAL
3.3V BUS
EXTERNAL
BUS GND
DD
.
Hardware Power-Down
Thermal Shutdown
Watchdog
21