MAX5980GTJ+T Maxim Integrated, MAX5980GTJ+T Datasheet - Page 27

• Manufacturer Part Number: MAX5980GTJ+T
• Description: Power Switch ICs - POE / LAN 0-16V Hot-Swap Controller
• Manufacturer: Maxim Integrated

Specifications of MAX5980GTJ+T

• Rohs: yes
• Number Of Switches: Quad
• Off Time (max): 0.1 ms
• Operating Supply Voltage: 32 V to 60 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 2758.6 mW
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 5 mA

Table 5. Register Map Summary (continued)
STATUS
CONFIGURATION
PUSHBUTTONS
GENERAL
ADDR
0Ch
0Dh
1Ah
1Bh
1Ch
1Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Eh
1Fh
Operating Mode R/W
Midspan Enable R/W
Configuration 1
Class 5 Enable
Miscellaneous
Detection and
Power-Enable
Programming
Programming
Power Status
Classification
Classification
Port 1 Status
Port 2 Status
Port 3 Status
Port 4 Status
REGISTER
Disconnect
Pushbutton
Pushbutton
Pushbutton
Pin Status
Detection/
Reserved
Reserved
TLIM1/2
TLIM3/4
Enable
Enable
NAME
Global
ID
TYPE
R/W
R/W CLASS_EN4 CLASS_EN3 CLASS_EN2 CLASS_EN1
R/W
R/W
R/W
R/W
R/W
—
W
W
W
R
R
R
R
R
R
R
ID_CODE[4] ID_CODE[3] ID_CODE[2] ID_CODE[1] ID_CODE[0]
PWR_OFF4
ACD_EN4
PGOOD4
CLS_PB4
INT_CLR
TLIM2[3]
TLIM4[3]
P4_M[1]
INT_EN
Quad, IEEE 802.3at/af PSE Controller
BIT 7
—
—
—
—
—
—
—
—
—
PWR_OFF3
CLASS1[2]
CLASS2[2]
CLASS3[2]
CLASS4[2]
ACD_EN3
DET_CHG
PGOOD3
CLS_PB3
PIN_CLR
TLIM2[2]
TLIM4[2]
P4_M[0]
BIT 6
—
—
—
—
—
PWR_OFF2
CLASS1[1]
CLASS2[1]
CLASS3[1]
CLASS4[1]
ACD_EN2
PGOOD2
SLAVE[1]
CLS_PB2
TLIM2[1]
TLIM4[1]
P3_M[1]
BIT 5
—
—
—
—
—
—
PWR_OFF1
CLASS1[0]
CLASS2[0]
CLASS3[0]
CLASS4[0]
ACD_EN1
RESET_IC
SLAVE[0]
PGOOD1
CLS_PB1
TLIM2[0]
TLIM4[0]
P3_M[0]
BIT 4
for Power-over-Ethernet
—
—
—
—
—
MIDSPAN4
PWR_ON4
RESET_P4
PWR_EN4
DCD_EN4
DET_EN4
DET_PB4
CL5_EN4
TLIM1[3]
TLIM3[3]
P2_M[1]
BIT 3
ID[1]
—
—
—
—
—
—
—
DET_ST1[2] DET_ST1[1] DET_ST1[0]
DET_ST2[2] DET_ST2[1] DET_ST2[0]
DET_ST3[2] DET_ST3[1] DET_ST3[0]
DET_ST4[2] DET_ST4[1] DET_ST4[0]
MIDSPAN3
PWR_ON3
RESET_P3
PWR_EN3
DCD_EN3
DET_EN3
DET_PB3
CL5_EN3
TLIM1[2]
TLIM3[2]
P2_M[0]
REV[2]
BIT 2
ID[0]
—
—
—
MIDSPAN2
PWR_ON2
RESET_P2
PWR_EN2
DCD_EN2
DET_EN2
DET_PB2
CL5_EN2
TLIM1[1]
TLIM3[1]
P1_M[1]
REV[1]
BIT 1
—
—
—
—
MIDSPAN1
PWR_ON1
RESET_P1
PWR_EN1
DCD_EN1
DET_EN1
DET_PB1
CL5_EN1
TLIM1[0]
TLIM3[0]
P1_M[0]
REV[0]
AUTO
BIT 0
—
—
—
XXXX–XXXX
XXXX–XXXX
00XX–XX0X
XXXX–0000
0000–XXXX
0000–0000
0000–0000
0000–0000
0000–0000
0000–0000
1010–0000
0000–0000
0000–0000
0000–0000
1101–0000
0000–0000
0000–0000
0000–0000
RESET
STATE
—
—
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