MAX5980GTJ+T Maxim Integrated, MAX5980GTJ+T Datasheet - Page 23

• Manufacturer Part Number: MAX5980GTJ+T
• Description: Power Switch ICs - POE / LAN 0-16V Hot-Swap Controller
• Manufacturer: Maxim Integrated

Specifications of MAX5980GTJ+T

• Rohs: yes
• Number Of Switches: Quad
• Off Time (max): 0.1 ms
• Operating Supply Voltage: 32 V to 60 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 2758.6 mW
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 5 mA

Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from
high to low while SCL is high. When the master finishes
communicating with the slave, the master issues a STOP
(P) condition by transitioning SDA from low to high while
SCL is high. The STOP condition frees the bus for anoth-
er transmission (see Figure 6).
Each clock pulse transfers one data bit (Figure 7). The
data on SDA must remain stable while SCL is high.
Figure 6. START and STOP Conditions
Figure 8. Acknowledge
SDAIN
SDA/
SCL
START
S
BY TRANSMITTER
SDA/SDAOUT
BY RECEIVER
SDA/SDAIN
SCL
START CONDITION
START and STOP Conditions
Quad, IEEE 802.3at/af PSE Controller
S
1
Bit Transfer
STOP
P
2
for Power-over-Ethernet
The acknowledge bit is a clocked 9th bit (Figure 8) that
the recipient uses to handshake receipt of each byte of
data. Thus, each byte transferred effectively requires
9 bits. The master generates the 9th clock pulse, and
the recipient pulls down SDA during the acknowledge
clock pulse, so the SDA line is stable low during the high
period of the clock pulse. When the master transmits to
the MAX5980, the device generates the acknowledge
bit. When the device transmits to the master, the master
generates the acknowledge bit.
Figure 7. Bit Transfer
SDA/SDAIN
SCL
CLOCK PULSE FOR ACKNOWLEDGMENT
DATA LINE STABLE;
DATA VALID
8
DATA ALLOWED
CHANGE OF
9
Acknowledge
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