MAX5980GTJ+T Maxim Integrated, MAX5980GTJ+T Datasheet - Page 31

• Manufacturer Part Number: MAX5980GTJ+T
• Description: Power Switch ICs - POE / LAN 0-16V Hot-Swap Controller
• Manufacturer: Maxim Integrated

Specifications of MAX5980GTJ+T

• Rohs: yes
• Number Of Switches: Quad
• Off Time (max): 0.1 ms
• Operating Supply Voltage: 32 V to 60 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 2758.6 mW
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 5 mA

The Interrupt Mask register (R01h, Table 7) contains
mask bits that suppress the corresponding interrupt
bits in register R00h (active-high). Setting mask bits low
individually disables the corresponding interrupt signal.
When masked (set low), the corresponding bits are still
set in the Interrupt register (R00h) but the masking bit
(R01h) suppresses the generation of an interrupt signal
(INT). Supply interrupts set on a power-up or reset event
cannot be masked, such as TSD, V
UVLO
Mask register is set to a default state of E4h if AUTO is
high, and 80h is AUTO is low.
Table 7. Interrupt Mask Register
Table 8. Power Event Register
TCUT_MASK
SUP_MASK
CLS_MASK
DET_MASK
TST_MASK
DIS_MASK
PG_MASK
PG_CHG4
PG_CHG3
PG_CHG2
PG_CHG1
PE_MASK
PE_CHG4
PE_CHG3
PE_CHG2
PE_CHG1
SYMBOL
SYMBOL
. On power-up or a reset condition, the Interrupt
ADDRESS =
ADDRESS = 01h
BIT NO.
BIT NO.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Interrupt Mask Register (R01h)
Quad, IEEE 802.3at/af PSE Controller
TYPE
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
02h
R
R
R
R
R
R
R
R
DD_UVLO
Supply interrupt mask. A logic-high enables the SUP_INT interrupt. A logic-low
disables the SUP_INT interrupts.
Startup interrupt mask. A logic-high enables the TST_INT interrupt. A logic-low
disables the TST_INT interrupts.
Current interrupt mask. A logic-high enables the TCUT_INT interrupt. A logic-low
disables the TCUT_INT interrupt.
Classification interrupt mask. A logic-high enables the CLS_INT interrupt. A logic-low
disables the CLS_END interrupt.
Detection interrupt mask. A logic-high enables the DET_INT interrupt. A logic-low
disables the DET_INT interrupt.
DC disconnect interrupt mask. A logic-high enables the DIS_INT interrupts. A logic-
low disables the DIS_INT interrupts.
PGOOD interrupt mask. A logic-high enables the PG_INT interrupts. A logic-low
disables the PG_INT interrupts.
Power-enable interrupt mask. A logic-high enables the PE_INT interrupts. A logic-low
disables the PE_INT interrupts.
TYPE
CoR
CoR
CoR
CoR
CoR
CoR
CoR
CoR
03h
, and V
PGOOD change event for port 4
PGOOD change event for port 3
PGOOD change event for port 2
PGOOD change event for port 1
Power enable change event for port 4
Power enable change event for port 3
Power enable change event for port 2
Power enable change event for port 1
EE_
for Power-over-Ethernet
The Power Event register (R02h/R03h, Table 8) records
changes in the power status of the port. On power-
up or after a reset condition, the Power Event reg-
ister is set to a default value of 00h. Any change in
PGOOD_ (R10h[7:4]) sets PG_CHG_ to 1. Any change in
PWR_EN_ (R10h[3:0]) sets PE_CHG_ to 1. PG_CHG_
and PE_CHG_ trigger on the transition edges of PGOOD_
and PWR_EN_, and do not depend on the actual logic
status of the bits. The Power Event register has two
addresses. When read through the R02h address, the
content of the register is left unchanged. When read
through the Clear on Read (CoR) R03h address, the
register content is reset to the default state.
DESCRIPTION
DESCRIPTION
Event Registers (R02h–R08h)
Power Event Register (R02h/R03h)
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