MAX5980GTJ+T Maxim Integrated, MAX5980GTJ+T Datasheet - Page 44

• Manufacturer Part Number: MAX5980GTJ+T
• Description: Power Switch ICs - POE / LAN 0-16V Hot-Swap Controller
• Manufacturer: Maxim Integrated

Specifications of MAX5980GTJ+T

• Rohs: yes
• Number Of Switches: Quad
• Off Time (max): 0.1 ms
• Operating Supply Voltage: 32 V to 60 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 2758.6 mW
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 5 mA

Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
Table 36. Watchdog Register
Table 37. Developer ID/Revision Number Register
These registers are at this time reserved. Writing to these
registers will have no effect (the address autoincrement
will still update) and any attempt to read these registers
will return all zeroes.
The Firmware register (R41h) is at this time set by default
set to 00h. This register is provided so that it can be
reprogrammed as needed by the software to indicate the
version of the device firmware.
The Watchdog register (R42h, Table 36) is used to
monitor device status, and to enable and monitor the
watchdog functionality. On a power-up or after a reset
44
Reserved Registers (R40h, R45h, R4Ah, R4Fh, R54h,
DEV_REV[2:0]
WD_DIS[3:0]
DEV_ID[2:0]
WD_STAT
SYMBOL
Reserved
SYMBOL
Reserved
Reserved
Other Functions Registers (R00h, R01h)
VEE_OV
VEE_UV
R59h, R5Ah, R5Bh, R5Ch, R5Dh, R5Eh, R5Fh)
ADDRESS = 42h
ADDRESS = 43h
BIT NO.
BIT NO.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Watchdog Register (R42h)
Firmware Register (R41h)
TYPE
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
Developer software-assigned ID number
Reserved
Reserved
Developer software-assigned revision number
Reserved.
VEE_OV is set if V
VEE_UV is set if V
Watchdog Disable. When WD_DIS[3:0] is set to 1011 (default), the watchdog is dis-
abled. Any other setting enables the watchdog.
WD_STAT is set to 1 when the watchdog timer expires.
AGND
AGND
- V
- V
condition, this register is set to a default value of 16h.
V
dent of the Power Status register. WD_DIS[3:0] is set
by default to 1011, disabling the watchdog timeout. Set
WD_DIS[3:0] to any other value to enable the watchdog.
The watchdog monitors the SCL line for activity. If there
are no transitions for 2.5s (typ) the WDSTAT bit is set to
1 and all ports are powered down (using the individual
port reset protocol). WD_STAT must be reset before any
port can be reenabled.
The Developer ID/Revision Number register (R43h,
Table 37) is provided to allow developers using this
device to assign the design an ID and revision version
number unique to their software/design. On a power-up
or after a reset condition, this register is set to a default
value of 00h.
EE_OV
EE
EE
< 40V.
> 62V.
Developer ID/Revision Number Register (R43h)
and V
DESCRIPTION
DESCRIPTION
EE_UV
provide supply status indepen-