MAX5980GTJ+T Maxim Integrated, MAX5980GTJ+T Datasheet - Page 47

• Manufacturer Part Number: MAX5980GTJ+T
• Description: Power Switch ICs - POE / LAN 0-16V Hot-Swap Controller
• Manufacturer: Maxim Integrated

Specifications of MAX5980GTJ+T

• Rohs: yes
• Number Of Switches: Quad
• Off Time (max): 0.1 ms
• Operating Supply Voltage: 32 V to 60 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 2758.6 mW
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 5 mA

Careful PCB layout is critical to achieve high efficiency
and low EMI. Follow these layout guidelines for optimal
performance:
1) Place the high-frequency input bypass capacitor (0.1FF
2) Use large SMT component pads for power dissipat-
3) For the best accuracy current sensing, use Kelvin-
Figure 14. Kelvin-Sense Layout Diagram
___________Applications Information
ceramic capacitor from AGND to V
bypass capacitors (0.1FF ceramic capacitors from
AGND to OUT_) as close to the device as possible.
ing devices such as the MAX5980 and the external
MOSFETs and sense resistors in the high-power path.
sense techniques for the SENSE_ and SVEE_ inputs
in the PCB layout. The device provides individual
high-side SENSE_ inputs for each port, and two sepa-
rate shared low-side sense returns, SVEE1 (ports 1
and 2 low-side sense input) and SVEE2 (ports 3 and
4 low-side sense input). The high-side sensing should
SENSE1
SENSE2
Quad, IEEE 802.3at/af PSE Controller
R
R
SENSE2
SENSE1
Layout Procedure
EE
SVEE1
) and the output
KELVIN-SENSE TRACES TO HIGH-SIDE/LOW-SIDE SENSE INPUTS
VIAS TO V
CURRENT
CURRENT
PORT
PATH
PORT
PATH
for Power-over-Ethernet
EE
4) Use short, wide traces whenever possible for high-
5) Use the MAX5980 Evaluation Kit as a design and
6) The exposed pad (EP) must be soldered evenly to
be done from the end of the high-side sense resistor
pad, and the SVEE_ pairs should be routed from the
end of the low-side sense resistor pads. To minimize
the impact from additional series resistance, the two
end points should be as close as possible, and sense
trace length should be minimized (see Figure 14 for a
layout diagram, and refer to the MAX5980 Evaluation
Kit for a design example).
power paths.
layout reference.
the PCB ground plane (V
and power dissipation. Use multiple vias beneath
the exposed pad for maximum heat dissipation. A
1.0mm to 1.2mm pitch is the recommended spacing
for these vias and they should be plated (1oz copper)
with a small barrel diameter (0.30mm to 0.33mm).
SVEE2
R
R
SENSE3
SENSE3
SENSE4
EE
) for proper operation
SENSE4
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