MAX5980GTJ+T Maxim Integrated, MAX5980GTJ+T Datasheet - Page 35

• Manufacturer Part Number: MAX5980GTJ+T
• Description: Power Switch ICs - POE / LAN 0-16V Hot-Swap Controller
• Manufacturer: Maxim Integrated

Specifications of MAX5980GTJ+T

• Rohs: yes
• Number Of Switches: Quad
• Off Time (max): 0.1 ms
• Operating Supply Voltage: 32 V to 60 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 2758.6 mW
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 5 mA

Table 16. Power Status Register
Table 17. Pin Status Register
Table 18. PSE-ICM Port Control Mapping
The Power Status register (R10h, Table 16) records
the current status of port power. On power-up or after
a reset condition, the port is initially unpowered and
the Power Status register is set to its default value of
00h. PGOOD_ (R10h[7:4]) is set to 1 at the end of the
power-up startup period if V
than t
0 whenever V
occurs. PWR_EN_ (R10h[3:0]) is set to 1 when the port
power is turned on. PWR_EN resets to 0 as soon as the
port turns off. Any transition of PGOOD_ and PWR_EN_
bits set the corresponding bit in the Power Event register
(R02h/R03h, Table 8).
SLAVE[1:0]
PWR_EN4
PWR_EN3
PWR_EN2
PWR_EN1
SYMBOL
PGOOD4
PGOOD3
PGOOD2
PGOOD1
SYMBOL
Reserved
Reserved
Reserved
PGOOD
ID[1:0]
AUTO
SLAVE[1:0]
ADDRESS = 10h
ADDRESS = 11h
. PGOOD_ is a real-time bit and is reset to
OUT_
00
01
10
11
BIT NO.
- V
BIT NO.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
EE
Power Status Register (R10h)
Quad, IEEE 802.3at/af PSE Controller
P PG
OUT_
TYPE
TYPE
TH
Slave device controls ports A, B, C, and D
Slave device controls ports E, F, G, and H
Slave device controls ports I, J, K, and L
Slave device controls ports M, N, O, and P
—
—
—
R
R
R
R
R
R
R
R
R
R
R
R
R
- V
, or a fault condition
EE
Power-good condition on port 4
Power-good condition on port 3
Power-good condition on port 2
Power-good condition on port 1
Power is enabled on port 4
Power is enabled on port 3
Power is enabled on port 2
Power is enabled on port 1
Reserved
Reserved
Slave input (A1 and A0) latched-in status (Table 3)
ID input (A3 and A2) latched-in status (Table 3)
Reserved
AUTO input latched-in status
> PG
TH
for more
for Power-over-Ethernet
PSE-ICM PORTS CONTROLLED
The Pin Status register (R11h, Table 17) records the state
of the A3, A2, A1, A0, and AUTO pins. The states of A3
and A2 (into ID[1:0]), A1 and A0 (into SLAVE[1:0]), and
AUTO are latched into their corresponding bits after a
power-up or reset condition clears. Therefore, the default
state of the Pin Status register depends on those inputs
(00XX–XX0X). Changes to those inputs during normal
operation are ignored and do not change the register
contents. A3, A2, A1, and A0 all have internal pullups,
and when left unconnected result in a default address of
0101111 (2Fh). Connect one or more low before a power-
up or device reset to reprogram the slave address.
SLAVE[1:0] also typically indicates which of the 16
PSE-ICM ports the slave device controls (Table 18).
DESCRIPTION
DESCRIPTION
Pin Status Register (R11h)
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