MAX5980GTJ+T Maxim Integrated, MAX5980GTJ+T Datasheet - Page 29

• Manufacturer Part Number: MAX5980GTJ+T
• Description: Power Switch ICs - POE / LAN 0-16V Hot-Swap Controller
• Manufacturer: Maxim Integrated

Specifications of MAX5980GTJ+T

• Rohs: yes
• Number Of Switches: Quad
• Off Time (max): 0.1 ms
• Operating Supply Voltage: 32 V to 60 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 2758.6 mW
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 5 mA

Table 5. Register Map Summary (continued)
X Indicates that the register reset state depends on either the status of the external programming pins (A3–A0, EN_CL5, AUTO,
— Indicates that the register is either unused or reserved. Always write a logic-low to any reserved bits when programming a reg-
ADDR
4Ch
4Dh
5Ch
5Dh
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Eh
5Fh
and MIDSPAN) or that the cause of the reset condition determines the state.
ister, unless otherwise indicated in the Register Map and Description section.
Port 1 GPMD
Power Status
Port 2 GPMD
Power Status
Port 3 GPMD
Power Status
Port 4 GPMD
Power Status
Port 1 High-
Port 2 High-
Port 3 High-
Port 4 High-
High-Power
Port 1 ICUT
Port 2 ICUT
Port 3 ICUT
Port 4 ICUT
REGISTER
ID/Revision
Port 1 ILIM
Port 2 ILIM
Port 3 ILIM
Port 4 ILIM
Developer
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Number
Enable
NAME
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—-
—
—
—
—
—
—
—
—
—
—
R
R
R
R
DEV_ID[2]
Quad, IEEE 802.3at/af PSE Controller
RDIS1
RDIS2
RDIS3
RDIS4
BIT 7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
CUT_RNG1
CUT_RNG2
CUT_RNG3
CUT_RNG4
DEV_ID[1]
ILIM1
ILIM2
ILIM3
ILIM4
BIT 6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DEV_ID[0]
ICUT1[5]
ICUT2[5]
ICUT3[5]
ICUT4[5]
BIT 5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
ICUT1[4]
ICUT2[4]
ICUT3[4]
ICUT4[4]
BIT 4
for Power-over-Ethernet
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
ICUT1[3]
ICUT2[3]
ICUT3[3]
ICUT4[3]
HP_EN4
BIT 3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
DEV_REV[2] DEV_REV[1] DEV_REV[0]
ICUT1[2]
ICUT2[2]
ICUT3[2]
ICUT4[2]
HP_EN3
BIT 2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
FET_BAD1
FET_BAD2
FET_BAD3
FET_BAD4
LEG_EN1
LEG_EN2
LEG_EN3
LEG_EN4
ICUT1[1]
ICUT2[1]
ICUT3[1]
ICUT4[1]
HP_EN2
BIT 1
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
PONG_EN1
PONG_PD1
PONG_EN2
PONG_PD2
PONG_EN3
PONG_PD3
PONG_EN4
PONG_PD4
ICUT1[0]
ICUT2[0]
ICUT3[0]
ICUT4[0]
HP_EN1
BIT 0
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0000–XXXX
0000–0000
0000–000X
XX01–0100
1000–0000
0000–0000
0000–000X
XX01–0100
1000–0000
0000–0000
0000–000X
XX01–0100
1000–0000
0000–0000
0000–000X
XX01–0100
1000–0000
0000–0000
RESET
STATE
—
—
—
—
—
—
—
—
—
—
—
29