MAX5980GTJ+T Maxim Integrated, MAX5980GTJ+T Datasheet - Page 37

• Manufacturer Part Number: MAX5980GTJ+T
• Description: Power Switch ICs - POE / LAN 0-16V Hot-Swap Controller
• Manufacturer: Maxim Integrated

Specifications of MAX5980GTJ+T

• Rohs: yes
• Number Of Switches: Quad
• Off Time (max): 0.1 ms
• Operating Supply Voltage: 32 V to 60 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 2758.6 mW
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 5 mA

Table 22. Detection and Classification Enable Register
The Detection and Classification Enable register (R14h,
Table 22) is used to enable detection and classification
routines for the ports. On a power-up or after a reset con-
dition, if AUTO = 1, this register is set to a default value
of FFh. If AUTO = 0, it is set to 00h.
While in Auto and Semiautomatic mode, setting DET_EN_
(R14h[3:0]) and CLASS_EN_ (R14h[7:4]) to 1 enables
load detection, and classification (upon successful
detection) respectively. In manual mode, R14h works
like a pushbutton register. Setting a bit high launches a
single detection or classification cycle, and at the con-
clusion of the cycle the bit then clears. In SHDN mode,
programming this register has no effect.
Table 23. Midspan Enable Register
Detection and Classification Enable Register (R14h)
CLASS_EN4
CLASS_EN3
CLASS_EN2
CLASS_EN1
MIDSPAN4
MIDSPAN3
MIDSPAN2
MIDSPAN1
SYMBOL
DET_EN4
DET_EN3
DET_EN2
DET_EN1
SYMBOL
Reserved
Reserved
Reserved
Reserved
ADDRESS = 14h
ADDRESS = 15h
BIT NO.
BIT NO.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Quad, IEEE 802.3at/af PSE Controller
TYPE
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
Enable classification on port 4
Enable classification on port 3
Enable classification on port 2
Enable classification on port 1
Enable detection on port 4
Enable detection on port 3
Enable detection on port 2
Enable detection on port 1
Reserved
Reserved
Reserved
Reserved
Enable cadence timing on port 4
Enable cadence timing on port 3
Enable cadence timing on port 2
Enable cadence timing on port 1
for Power-over-Ethernet
The Midspan Enable register (R15h, Table 23) is used
to control cadence timing (midspan) for the ports. On
a power-up or after a reset condition, this register is set
to a default value of 0000–XXXX where X is the latched-
in value of the MIDSPAN input. Setting MIDSPAN_
(R15h[3:0]) to 1 enables cadence timing where the port
backs off and waits at least 2s (min) after each failed
load detection. The IEEE 802.3at/af standard requires
a PSE that delivers power through the spare pairs (mid-
span) to have cadence timing (see the Midspan Mode
section for details).
Register R16h is at this time reserved. Writing to this
register has no effect (the address autoincrement still
updates) and any attempt to read this register returns
all zeroes.
DESCRIPTION
DESCRIPTION
Midspan Enable Register (R15h)
Reserved Register (R16h)
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