MAX5980GTJ+T Maxim Integrated, MAX5980GTJ+T Datasheet - Page 26

• Manufacturer Part Number: MAX5980GTJ+T
• Description: Power Switch ICs - POE / LAN 0-16V Hot-Swap Controller
• Manufacturer: Maxim Integrated

Specifications of MAX5980GTJ+T

• Rohs: yes
• Number Of Switches: Quad
• Off Time (max): 0.1 ms
• Operating Supply Voltage: 32 V to 60 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 2758.6 mW
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 5 mA

Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
When the device operates on a 3-wire interface with mul-
tiple masters, a master reading the device should use
repeated starts between the write that sets the device’s
address pointer, and the read(s) that take the data from
the location(s). It is possible for master 2 to take over
the bus after master 1 has set up the device’s address
pointer but before master 1 has read the data. If master
2 subsequently resets the device’s address pointer, then
master 1’s read may be from an unexpected location.
Table 4. Autoincrement Rules
Table 5. Register Map Summary
26
INTERRUPTS
EVENTS
ADDR
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
COMMAND BYTE ADDRESS RANGE
Fault Event CoR CoR
Interrupt Mask
Startup Event
Startup Event
Supply Event
Supply Event
Detect Event
Detect Event
Power Event
Power Event
REGISTER
Fault Event
Interrupt
NAME
CoR
CoR
CoR
CoR
0x00 to 0x71
0x71
TYPE
CoR
CoR
CoR
CoR
R/W
R
R
R
R
R
R
Operation with Multiple Masters
SUP_MASK
PG_CHG4
SUP_INT
BIT 7
CLS4
DIS4
ICV4
TSD
TST_MASK TCUT_MASK CLS_MASK
PG_CHG3
TST_INT
FETBAD
BIT 6
CLS3
DIS3
ICV3
Command address autoincrements after byte read or written
Command address remains at 0x71 after byte written or read
TCUT_INT
PG_CHG2
V
DD_UVLO
BIT 5
CLS2
DIS2
ICV2
PG_CHG1
V
CLS_INT
EE_UVLO
BIT 4
CLS1
DIS1
ICV1
Address autoincrementing allows the device to be con-
figured with fewer transmissions by minimizing the num-
ber of times the command address needs to be sent.
The command address stored in the device generally
increments after each data byte is written or read (Table
4). The device is designed to prevent overwrites on
unavailable register addresses and unintentional wrap-
around of addresses.
AUTOINCREMENT BEHAVIOR
DET_MASK
PE_CHG4
TSTART4
DET_INT
TCUT4
BIT 3
DET4
—
DIS_MASK
Command Address Autoincrementing
PE_CHG3
TSTART3
DIS_INT
TCUT3
BIT 2
DET3
—
PG_MASK
PE_CHG2
TSTART2
PG_INT
TCUT2
BIT 1
DET2
—
PE_MASK
PE_CHG1
TSTART1
PE_INT
TCUT1
BIT 0
DET1
—
1XX0–0X00
1000–0000
0000–0000
0000–0000
0000–0000
0000–0000
0000–0010
RESET
STATE