MT48LC32M8A2P-7E:D Micron Technology Inc, MT48LC32M8A2P-7E:D Datasheet - Page 58

• Manufacturer Part Number: MT48LC32M8A2P-7E:D
• Description: IC SDRAM 256MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC32M8A2P-7E:D

• Package / Case: 54-TSOP II
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (32M x 8)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Organization: 32Mx8
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Memory Configuration: 4 BLK (8M X 8)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 27: Alternating Bank Read Accesses
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Command
BA0, BA1
Address
DQM
CLK
CKE
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
Bank 0
T0
Row
Row
t CKH
t CMH
t AH
t AH
t AH
t RCD - bank 0
t RAS - bank 0
t RC - bank 0
t RRD
t CK
Note:
T1
NOP
1. For this example, BL = 4 and CL = 2.
Enable auto precharge
t CMS
t CL
Column m
Bank 0
T2
READ
t CMH
t CH
CL - bank 0
T3
NOP
t LZ
t AC
58
ACTIVE
Bank 3
T4
Row
Row
D
OUT
t OH
t AC
t RCD - bank 3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T5
D
NOP
OUT
t OH
t AC
Enable auto precharge
256Mb: x4, x8, x16 SDRAM
Column b
Bank 3
T6
READ
D
OUT
t OH
t AC
1
t RP - bank 0
CL - bank 3
© 1999 Micron Technology, Inc. All rights reserved.
T7
NOP
D
READ Operation
Don’t Care
OUT
t OH
t AC
Bank 0
Row
Row
T8
ACTIVE
D
OUT
t OH
t RCD - bank 0
Undefined
t AC