HYB18T512160BF-2.5 Qimonda, HYB18T512160BF-2.5 Datasheet

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HYB18T512160BF-2.5

Manufacturer Part Number
HYB18T512160BF-2.5
Description
IC DDR2 SDRAM 512MBIT 84TFBGA
Manufacturer
Qimonda
Datasheet

Specifications of HYB18T512160BF-2.5

Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
512M (32Mx16)
Speed
400MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 95°C
Package / Case
84-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
675-1016-2
November 2007
H YB 1 8 T 5 124 00 B F
H YB 1 8 T 5 128 00 B F
H YB 1 8 T 5 121 60 B F
5 1 2 - M b i t D o u b l e - D a t a - R a t e - T w o S D R A M
D D R 2 S D R A M
R o H S C o m p l i a n t P r o d u c t s
I n t e r n e t D a t a S h e e t
R e v . 1 . 2

Related parts for HYB18T512160BF-2.5

HYB18T512160BF-2.5 Summary of contents

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124 128 121 ...

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... We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com qag_techdoc_rev411 / 3.31 QAG / 2007-01-22 03292006-YBYM-WG0Z HYB18T512[40/80/16]0BF ...

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Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics. 1.1 Features The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: ± • 1.8 V 0.1 V Power Supply ± 1.8 ...

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QAG Speed Code DRAM Speed Grade DDR2 CAS-RCD-RP latencies f Max. CL3 CK3 Clock Frequency f CL4 CK4 f CL5 CK5 f CL6 CK6 t Min. RAS-CAS-Delay RCD t Min. Row Precharge Time RP t Min. Row Active Time RAS ...

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... Product Type Org. Speed Standard Temperature Range (0 °C - +85 °C) DDR2-800E( 6-6-6) ×8 HYB18T512800BF-2.5 DDR2-800E ×4 HYB18T512400BF-2.5 DDR2-800E ×16 HYB18T512160BF-2.5 DDR2-800E DDR2-800D( 5-5-5) ×8 HYB18T512800BF-25F DDR2-800D ×4 HYB18T512400BF-25F DDR2-800D ×16 HYB18T512160BF-25F DDR2-800D DDR2-667D( 5-5-5) ×8 HYB18T512800BF-3S DDR2-667D ×4 HYB18T512400BF-3S DDR2-667D ×16 HYB18T512160BF-3S ...

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Configuration This chapter contains the chip configuration. 2.1 Configuration for TFBGA-60 The chip configuration of a DDR2 SDRAM is listed by function in explained in Table 7 and Table 8 respectively. The ball numbering for the FBGA package is ...

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Ball# Name Ball Type Data Signals ×4 /×8 Organizations C8 DQ0 I/O C2 DQ1 I/O D7 DQ2 I/O D3 DQ3 I/O D1 DQ4 I/O D9 DQ5 I/O B1 DQ6 I/O B9 DQ7 I/O Data Strobe ×4 /×8 Organizations B7 DQS ...

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Abbreviation Description I Standard input-only ball. Digital levels O Output. Digital levels I/O I bidirectional input/output signal AI Input. Analog levels PWR Power GND Ground NC Not Connected Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_18) LV-CMOS Low ...

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V V Note: and are power and ground for the DLL. DDL SSDL V are isolated on the device. SSQ Rev. 1.2, 2007-11 03292006-YBYM-WG0Z HYB18T512[40/80/16]0BF 512-Mbit Double-Data-Rate-Two SDRAM Configuration for ×4 Components, TFBGA-60 (top view connected to ...

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Notes 1. RDQS / RDQS are enabled by EMRS(1) command RDQS / RDQS is enabled, the DM function is disabled 3. When enabled, RDQS & RDQS are used as strobe signals during reads and are ...

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Configuration for TFBGA-84 The chip configuration of a DDR2 SDRAM is listed by function in columns are explained in Table 7 and Table 8 Ball# Name Ball Type Clock Signals ×16 Organization ...

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Ball# Name Ball Type F1 DQ6 I/O F9 DQ7 I/O C8 DQ8 I/O C2 DQ9 I/O D7 DQ10 I/O D3 DQ11 I/O D1 DQ12 I/O D9 DQ13 I/O B1 DQ14 I/O B9 DQ15 I/O Data Strobe ×16 Organization B7 UDQS ...

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Abbreviation Description I Standard input-only ball. Digital levels. O Output. Digital levels. I/O I bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not Connected Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_18) LV-CMOS Low ...

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Notes 1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0] 2. LDM is the data mask signal for DQ[7:0], UDM is the data mask signal for DQ[15: and are power and ground for ...

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Addressing This chapter describes the DDR2 addressing. Configuration 128 Bank Address BA[1:0] Number of Banks 4 Auto Precharge A10 / AP Row Address A[13:0] Column Address A11, A[9:0] Number of Column Address Bits 11 Number of ...

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Functional Description This chapter contains the functional description. 3.1 DDR2 SDRAM Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. 1) Field Bits Type Description BA2 16 reg. addr. ...

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Field Bits Type Description Test Mode 0 TM Normal Mode Vendor specific test mode B CL [6:4] w CAS Latency Note: All other bit combinations are illegal. 011 100 CL ...

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Extended Mode Register EMR(1) The Extended Mode Register EMR(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, OCD program, ODT, DQS and output buffers disable, RDQS and RDQS enable. 1) Field Bits Type ...

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Field Bits Type Description AL [5:3] w Additive Latency Note: All other bit combinations are illegal. 000 B 001 B 010 B 011 B 100 B 101 B R 6,2 w Nominal Termination Resistance of ODT TT Note: See ...

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Extended Mode Register EMR(2) The Extended Mode Registers EMR(2) and EMR(3) are reserved for future use and must be programmed when setting the mode register during initialization. 1) Field Bits Type Description BA [15:14] w Bank Adress 00 BA ...

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Extended Mode Register EMR(3) The Extended Mode Register EMR(3) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0 when setting the mode register during initialization. 1) Field Bits Type Description BA2 ...

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Burst Mode Operation Burst Length Starting Address (A2 A1 A0) × × ×1 0 × ...

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Truth Tables This chapter describes the truth tables. Function CKE Previous Cycle (Extended) Mode Register Set H Auto-Refresh H Self-Refresh Entry H Self-Refresh Exit L Single Bank Precharge H Precharge all Banks H Bank Activate H Write H Write ...

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Current State CKE Previous Cycle (N-1) Power-Down L L Self Refresh L L Bank(s) Active H All Banks Idle H H Any State other than H listed above 1) Current state is the state of the DDR2 SDRAM immediately ...

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Electrical Characteristics This chapter describes the Electrical Characteristics. 5.1 Absolute Maximum Ratings Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Symbol Parameter V V Voltage on pin relative ...

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DC Characteristics Symbol Parameter V Supply Voltage DD V Supply Voltage for DLL DDDL V Supply Voltage for Output DDQ V Input Reference Voltage REF V Termination Voltage tracks with , tracks with ...

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DC & AC Characteristics DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The ...

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Symbol Parameter V DC input signal voltage IN(dc differential input voltage ID(dc differential input voltage ID(ac differential cross point input voltage IX(ac) AC differential cross point output voltage 0.5 × V OX(ac ...

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Output Buffer Characteristics This chapter describes the Output Buffer Characteristics. Symbol Parameter I Output Minimum Source DC Current OH I Output Minimum Sink DC Current 1 1. – ...

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Input / Output Capacitance This chapter contains the Input / Output Capacitance. Symbol Parameter CCK Input capacitance, CK and CK CDCK Input capacitance delta, CK and CK CI Input capacitance, all other input-only pins CDI Input capacitance delta, all ...

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Overshoot and Undershoot Specification This chapter contains Overshoot and Undershoot Specification. AC Overshoot / Undershoot Specification for Address and Control Pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area V Maximum overshoot ...

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AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area V Maximum overshoot area above DDQ V Maximum undershoot area below SSQ AC ...

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Currents Measurement Conditions This chapter describes the Current Measurement, Specifications and Conditions. Parameter Operating Current - One bank Active - Precharge CK(IDD) RC RC(IDD) RAS RAS.MIN(IDD) Address ...

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Parameter Self-Refresh Current CKE ≤ 0.2 V; external clock off, CK and Other control and address inputs are floating, Data bus inputs are floating. Operating Bank Interleave Read Current I 1. All banks interleaving reads, = ...

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Symbol –25F –2.5 DDR2-800D DDR2-800E Max. Max DD0 I 105 100 DD0 I 100 95 DD1 I 120 115 DD1 DD2P DD2N DD2Q DD3P_0 (fast) ...

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Timing Characteristics This chapter contains speed grade definition, AC timing parameter and ODT tables. 7.1 Speed Grade Definitions Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Symbol t Clock Period @ ...

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Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Symbol Min. t Clock Period @ Row Active Time RAS t Row Cycle Time RC ...

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Component AC Timing Parameters DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667 Parameter DQ output access time from CAS to CAS command delay Average clock high pulse width Average clock period CKE minimum ...

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Parameter Mode register set command cycle time OCD drive mode output delay DQ/DQS output hold time from DQS DQ hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Read preamble Read postamble ...

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New units, ‘ ‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘ CK.AVG under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and t ...

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The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C and 95 °C. T ≤ 85 °C. 28) 0 °C≤ CASE T 29) 85 °C < ≤ ...

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DRAM Component Timing Parameter by Speed Grade - DDR2–533 and DDR2–400 Parameter Symbol t DQ output access time from CAS A to CAS B command period CCD t CK, CK high-level width CH t CKE ...

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Parameter Symbol t Address and control input pulse IPW width (each input) t Address and control input setup time IS.BASE t DQ low-impedance time from CK / LZ(DQ DQS low-impedance from LZ(DQS) t MRS command ...

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Parameter Symbol t Exit Self-Refresh to non-Read XSNR command t Exit Self-Refresh to Read command XSRD Write recovery time for write with WR Auto-Precharge 1.8 V ± 0.1V; = 1.8 V ± 0.1 V. DDQ DD ...

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Rev. 1.2, 2007-11 03292006-YBYM-WG0Z HYB18T512[40/80/16]0BF 512-Mbit Double-Data-Rate-Two SDRAM Method for Calculating Transitions and Endpoint Differential Input Waveform Timing - 45 Internet Data Sheet FIGURE 8 FIGURE and DS DH ...

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Rev. 1.2, 2007-11 03292006-YBYM-WG0Z HYB18T512[40/80/16]0BF 512-Mbit Double-Data-Rate-Two SDRAM Differential Input Waveform Timing - 46 Internet Data Sheet FIGURE and lS lH ...

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Jitter Definition and Clock Jitter Specification Generally, jitter is defined as “the short-term variation of a signal with respect to its ideal position in time”. The following table provides an overview of the terminology. Symbol Parameter t Average clock ...

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Symbol Parameter t Cumulative error ERR.nPER across n cycles t Average high-pulse CH.AVG width t Average low-pulse CL.AVG width t Duty-cycle jitter JIT.DUTY The following parameters are specified per their average values however understood that the following relationship ...

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Symbol Parameter Min Clock period CK.ABS t t Clock high-pulse width CH.ABS t t Clock low-pulse width CL.ABS t Example: for DDR2-667, = (0.48 x 3000ps) – 125 ps = 1315 ps = 0.438 x 3000 ps. CH.ABS.MIN ...

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ODT AC Electrical Characteristics This chapter describes the ODT AC electrical characteristics. ODT AC Characteristics and Operating Conditions for DDR2-667 , DDR2-800 Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down ...

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Package Outline This chapter contains the package dimension figures. Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.2, 2007-11 03292006-YBYM-WG0Z HYB18T512[40/80/16]0BF 512-Mbit Double-Data-Rate-Two SDRAM Package Outline PG-TFBGA-60 51 Internet Data ...

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Rev. 1.2, 2007-11 03292006-YBYM-WG0Z HYB18T512[40/80/16]0BF 512-Mbit Double-Data-Rate-Two SDRAM Package Outline PG-TFBGA-84 52 Internet Data Sheet FIGURE 12 ...

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... Product Nomenclature For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter. Example for Field Number 1 2 DDR2 DRAM HYB 18 Field Description 1 Qimonda Component Prefix 2 Interface Voltage [V] 3 DRAM Technology 4 Component Density [Mbit] 5 Number of I/Os 6 Product Variations 7 Die Revision 8 Package, Lead-Free Status ...

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Field Description 10 Speed Grade Rev. 1.2, 2007-11 03292006-YBYM-WG0Z 512-Mbit Double-Data-Rate-Two SDRAM Values Coding –19F DDR2–1066 6–6–6 –1.9 DDR2–1066 7–7–7 –25F DDR2–800 5–5–5 –2.5 DDR2–800 6–6–6 –3 DDR2–667 4–4–4 –3S DDR2–667 5–5–5 –3.7 DDR2–533 4–4–4 –5 DDR2–400 3–3–3 54 Internet ...

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List of Illustrations Configuration for ×4 Components, TFBGA-60 (top view ...

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... Clock-Jitter Specifications for –667, –800 Table 42 ODT AC Characteristics and Operating Conditions for DDR2-667 , DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . 50 Table 43 ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . 50 Table 44 Examples for Nomenclature Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 45 DDR2 Memory Components Rev. 1.2, 2007-11 03292006-YBYM-WG0Z 512-Mbit Double-Data-Rate-Two SDRAM = 000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2 001 ...

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Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system ...

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