HYB18T512160BF-2.5 Qimonda, HYB18T512160BF-2.5 Datasheet - Page 24

• Manufacturer Part Number: HYB18T512160BF-2.5
• Description: IC DDR2 SDRAM 512MBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T512160BF-2.5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1016-2

1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)
3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
4) CKE must be maintained HIGH while the device is in OCD calibration mode.
5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh
8) “X” means “don’t care (including floating around
9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
11)
12)
13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the
14) Valid commands for Self Refresh Exit are NOP and DESELCT only.
15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or
16) Self Refresh mode can only be entered from the All Banks Idle state.
17) Must be a legal command as defined in the Command Truth Table.
1) Used to mask write data; provided coincident with the corresponding data.
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
Current State
Power-Down
Self Refresh
Bank(s) Active
All Banks Idle
Any State other than
listed above
Name (Function)
Write Enable
Write Inhibit
and then restarted through the specified initialization sequence before normal operation can continue.
requirements
Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).
t
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of
V
commands may be issued only after
Refresh operations are in progress.
CKE.MIN
REF
must be maintained during Self Refresh operation.
of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
1)
t
IS
+ 2 ×
CKE
Previous Cycle
(N-1)
L
L
L
L
H
H
H
H
t
CK
+
t
IH
.
t
XSRD
6)
(200 clocks) is satisfied.
Current Cycle
(N)
L
H
L
H
L
L
L
H
V
REF
)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in
Clock Enable (CKE) Truth Table for Synchronous Transitions
6)
24
Command
(N)
CS
X
DESELECT or NOP
X
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
AUTOREFRESH
Refer to the Command Truth Table
2)3)
RAS, CAS, WE,
512-Mbit Double-Data-Rate-Two SDRAM
DM
L
H
Action (N)
Maintain Power-Down
Power-Down Exit
Maintain Self Refresh
Self Refresh Exit
Active Power-Down Entry
Precharge Power-Down
Entry
Self Refresh Entry
Data Mask (DM) Truth Table
HYB18T512[40/80/16]0BF
Valid
X
2)
DQs
t
XSNR
Internet Data Sheet
period. Read
TABLE 16
TABLE 17
1)
Note
Note
7)8)11)
7)9)10)11)
8)11)12)
9)11)12)13)14)
7)9)10)11)15)
9)10)11)15)
7)11)14)16)
17)
4)5)