HYB18T512160BF-2.5 Qimonda, HYB18T512160BF-2.5 Datasheet - Page 33

• Manufacturer Part Number: HYB18T512160BF-2.5
• Description: IC DDR2 SDRAM 512MBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T512160BF-2.5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1016-2

6
This chapter describes the Current Measurement, Specifications and Conditions.
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
Parameter
Operating Current - One bank Active - Precharge
t
Address and control inputs are switching; Databus inputs are switching.
Operating Current - One bank Active - Read - Precharge
I
CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching;
Databus inputs are switching.
Precharge Power-Down Current
All banks idle; CKE is LOW;
are floating
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
Data bus inputs are switching
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
Data bus inputs are floating.
Active Power-Down Current
All banks open;
are floating. MRS A12 bit is set to 0 (Fast Power-down Exit).
Active Power-Down Current
All banks open;
are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
Active Standby Current
All banks open;
commands. Address inputs are switching; Data Bus inputs are switching;
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
switching; Data Bus inputs are switching;
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
t
switching; Data Bus inputs are switching;
Burst Refresh Current
t
commands, Other control and address inputs are switching, Data bus inputs are switching.
Distributed Refresh Current
t
valid commands, Other control and address inputs are switching, Data bus inputs are switching.
CK
OUT
RAS.MAX.(IDD)
RAS.MAX(IDD)
CK
CK
=
=
=
= 0 mA, BL = 4,
t
t
t
CK(IDD)
CK(IDD)
CK(IDD)
.
,
,
, Refresh command every
,
, Refresh command every
t
t
t
RP
RP
RC
t
t
t
=
CK
CK
CK
=
=
t
t
t
RP(IDD)
=
=
RP(IDD)
=
RC(IDD)
t
Currents Measurement Conditions
CK
t
t
t
CK(IDD)
CK(IDD)
CK(IDD)
=
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
t
,
CK(IDD)
t
RAS
, CKE is LOW; Other control and address inputs are stable; Data bus inputs
, CKE is LOW; Other control and address inputs are stable, Data bus inputs
;
t
t
CK
RAS
.
=
,
=
t
t
=
RC
t
RAS.MIN(IDD)
CK(IDD)
t
RAS.MAX(IDD)
=
t
t
t
RC(IDD)
RFC
REFI
;Other control and address inputs are stable; Data bus inputs
t
I
CK
t
=
OUT
CK
= 7.8 µs interval, CKE is LOW and CS is HIGH between
, CKE is HIGH, CS is HIGH between valid commands.
t
,
=
RFC(IDD)
=
t
RAS
t
= 0 mA.
,
CK(IDD)
t
t
CK(IDD)
RP
=
=
t
interval, CKE is HIGH, CS is HIGH between valid
RAS.MIN(IDD)
; Other control and address inputs are switching,
t
RP(IDD)
; Other control and address inputs are stable,
; CKE is HIGH, CS is HIGH between valid
33
,
t
RCD
=
t
RCD(IDD)
(IDD)
(IDD)
, AL = 0, CL = CL(IDD);
512-Mbit Double-Data-Rate-Two SDRAM
;
;
t
t
CK
CK
=
=
t
t
CK(IDD)
CK(IDD)
I
DD
Measurement Conditions
;
;
HYB18T512[40/80/16]0BF
t
t
RAS
RAS
=
=
Internet Data Sheet
Symbol
I
I
I
I
I
I
I
I
I
I
I
I
DD0
DD1
DD2P
DD2N
DD2Q
DD3P(0)
DD3P(1)
DD3N
DD4R
DD4W
DD5B
DD5D
TABLE 32
Note
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