HYB18T512160BF-2.5 Qimonda, HYB18T512160BF-2.5 Datasheet - Page 27

• Manufacturer Part Number: HYB18T512160BF-2.5
• Description: IC DDR2 SDRAM 512MBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T512160BF-2.5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1016-2

5.3
DDR2 SDRAM pin timing are specified for either single ended
or differential mode depending on the setting of the EMRS(1)
“Enable DQS” mode bit; timing advantages of differential
mode are realized in system design. The method by which the
DDR2 SDRAM pin timing are measured is mode dependent.
In single ended mode, timing relationships are measured
relative to the rising or falling edges of DQS crossing at
1) Input waveform timing is referenced to the input signal crossing through the
2) The input signal minimum Slew Rate is to be maintained over the range from
3) AC timings are referenced with input waveforms switching from
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
Symbol
V
V
V
V
Symbol
V
V
SLEW
IH(dc)
IL(dc)
IH(ac)
IL(ac)
REF
SWING.MAX
to
transitions.
V
IL(ac).MAX
for falling edges as shown in
Parameter
DC input logic HIGH
DC input LOW
AC input logic HIGH
AC input LOW
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum Slew Rate
Condition
DC & AC Characteristics
Figure 4
DDR2-667, DDR2-800
V
–0.3
V
—
Min.
REF
REF
+ 0.125
+ 0.200
V
REF
V
.
IL(ac)
27
to
In differential mode, these timing relationships are measured
relative to the crosspoint of DQS and its complement, DQS.
This distinction in timing methods is verified by design and
characterization but not subject to production test. In single
ended mode, the DQS (and RDQS) signals are internally
disabled and don’t care.
Max.
V
V
—
V
V
DDQ
REF
REF
IH(ac)
– 0.125
– 0.200
+ 0.3
V
on the positive transitions and
REF
V
IH(ac).MIN
level applied to the device under test.
Value
0.5 x
1.0
1.0
Single-ended AC Input Test Conditions
512-Mbit Double-Data-Rate-Two SDRAM
to
V
DDR2-533, DDR2-400
V
–0.3
V
—
V
Min.
DDQ
REF
REF
REF
for rising edges and the range from
+ 0.125
+ 0.250
DC & AC Logic Input Levels
HYB18T512[40/80/16]0BF
V
IH(ac)
Max.
V
V
—
V
DDQ
REF
REF
Internet Data Sheet
Unit
V
V
V / ns
to
– 0.125
- 0.250
V
+ 0.3
IL(ac)
TABLE 23
TABLE 24
on the negative
Notes
1)
1)
2)3)
Units
V
V
V
V
V
REF