HYB18T512160BF-2.5 Qimonda, HYB18T512160BF-2.5 Datasheet - Page 50

• Manufacturer Part Number: HYB18T512160BF-2.5
• Description: IC DDR2 SDRAM 512MBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T512160BF-2.5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1016-2

7.4
This chapter describes the ODT AC electrical characteristics.
1) New units, “
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
Symbol
t
t
t
t
t
t
t
t
Symbol
t
t
t
t
t
t
t
t
AOND
AON
AONPD
AOFD
AOF
AOFPD
ANPD
AXPD
AOND
AON
AONPD
AOFD
AOF
AOFPD
ANPD
AXPD
under operation. Unit “
DDR2-533, “
be registered at
the ODT resistance is fully on. Both are measured from
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
Both are measured from
t
counting the actual input clock edges.
the ODT resistance is fully on. Both are measured from
10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if
Both are measured from
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if
AOFD
is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by
Parameter / Condition
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
Parameter / Condition
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
CK.AVG
t
CK
” is used for both concepts. Example:
T
m
” and “
+ 2, even if (
ODT AC Electrical Characteristics
n
CK
n
t
t
AOFD
AOFD
” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
CK
”, are introduced in DDR2-667 and DDR2-800 Unit “
, which is interpreted differently per speed bin. For DDR2-667/800, if
. Both are measured from
T
ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400
ODT AC Characteristics and Operating Conditions for DDR2-667 , DDR2-800
m
+ 2 -
T
m
) is 2 x
t
CK.AVG
t
XP
t
t
= 2 [
t
AOND
AOND
AOFD
+
t
n
ERR.2PER(Min)
, which is interpreted differently per speed bin. For DDR2-667/800
, which is interpreted differently per speed bin. For DDR2-400/533,
, which is interpreted differently per speed bin. For DDR2-400/533,
CK
Values
Min.
2
t
t
t
t
3
8
Values
Min.
2
t
t
t
t
3
8
2.5
2.5
] means; if Power Down exit is registered at
AC.MIN
AC.MIN
AC.MIN
AC.MIN
AC.MIN
AC.MIN
AC.MIN
AC.MIN
50
+ 2 ns
+ 2 ns
+ 2 ns
+ 2 ns
.
t
CK
= 5 ns.
t
CK
t
= 5 ns.
CK.AVG
Max.
2
t
2
2.5
t
2.5
—
—
Max.
2
t
2
2.5
t
2.5
—
—
AC.MAX
AC.MAX
AC.MAX
AC.MAX
512-Mbit Double-Data-Rate-Two SDRAM
t
t
CK
CK +
t
” represents the actual
t
CK
CK +
+
t
+ 0.7 ns
+ 0.6 ns
+ 1 ns
AC.MAX
+ 0.6 ns
t
+ t
AC.MAX
t
AC.MAX
AC.MAX
+ 1 ns
t
+ 1 ns
CK(avg)
+ 1 ns
+ 1 ns
HYB18T512[40/80/16]0BF
= 3 ns is assumed,
T
m
t
, an Active command may
CK.AVG
Unit
n
ns
ns
n
ns
ns
n
n
Unit
t
ns
ns
t
ns
ns
t
t
Internet Data Sheet
CK
CK
CK
CK
CK
CK
CK
CK
TABLE 42
TABLE 43
of the input clock
Note
1)
1)2)
1)
1)
1)3)
1)
1)
1)
Note
1)
2)
t
AOND
t
t
AOND
AOFD
is
is
is