HYB18T512160BF-2.5 Qimonda, HYB18T512160BF-2.5 Datasheet - Page 47

• Manufacturer Part Number: HYB18T512160BF-2.5
• Description: IC DDR2 SDRAM 512MBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T512160BF-2.5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1016-2

7.3
Generally, jitter is defined as “the short-term variation of a signal with respect to its ideal position in time”. The following table
provides an overview of the terminology.
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
Symbol
t
t
t
t
t
t
CK.AVG
JIT.PER
JIT
JIT.CC
JIT
ERR.2PER
(PER, LCK)
(CC, LCK)
Parameter
Average clock period
Clock-period jitter
Clock-period jitter
during DLL-locking
period
Cycle-to-cycle clock
period jitter
Cycle-to-cycle clock
period jitter during
DLL-locking period
Cumulative error
across 2 cycles
Jitter Definition and Clock Jitter Specification
Description
t
200-cycle window:
N = 200
t
t
t
t
t
period only.
t
t
consecutive clock cycles:
t
t
t
t
period only.
t
t
from
n = 2 for
where i = 1 to 200
CK.AVG
JIT.PER
JIT.PER
JIT.PER
JIT.PER
JIT
JIT
JIT.CC
JIT.CC
JIT.CC
JIT.CC
JIT
JIT
ERR.2PER
(PER,LCK) uses the same definition as
(PER,LCK) is not guaranteed through final production testing.
(CC,LCK) uses the same definition as
(CC,LCK) is not guaranteed through final production testing.
t
CK.AVG
is defined as the absolute difference in clock period between two
= Max of ABS{
defines the cycle - to - cycle jitter when the DLL is already locked.
is not guaranteed through final production testing.
tERR 2per
is calculated as the average clock period within any consecutive
is defined as the largest deviation of any single
= Min/Max of {
defines the single-period jitter when the DLL is already locked.
is not guaranteed through final production testing.
is defined as the cumulative error across 2 consecutive cycles
t
ERR
:
(2per)
47
t
t
CKi+1
CKi
Average Clock and Jitter Symbols and Definition
=
–
–
t
CK.AVG
t
i n 1
CKi
+
j
}
=
–
} where i = 1 to 200
i
512-Mbit Double-Data-Rate-Two SDRAM
tCK
t
JIT.CC
t
j
JIT.PER
–
n tCK avg
during the DLL-locking
, during the DLL-locking
HYB18T512[40/80/16]0BF
t
CK
from
Internet Data Sheet
t
CK.AVG
TABLE 39
:
Units
ps
ps
ps
ps
ps
ps