HYB18T512160BF-2.5 Qimonda, HYB18T512160BF-2.5 Datasheet - Page 23

• Manufacturer Part Number: HYB18T512160BF-2.5
• Description: IC DDR2 SDRAM 512MBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T512160BF-2.5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1016-2

4
This chapter describes the truth tables.
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means H or L (but a defined logic level)”.
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS and CKE at the rising edge of the clock.
5) Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode Register.
6) All banks must be in a precharged idle state, CKE must be high at least for
7)
8) Self Refresh Exit is asynchronous.
9) Burst reads or writes at BL = 4 cannot be terminated. See
10) The Power Down Mode does not perform any refresh operations.
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
Function
(Extended) Mode Register Set H
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
Single Bank Precharge
Precharge all Banks
Bank Activate
Write
Write with Auto-Precharge
Read
Read with Auto-Precharge
No Operation
Device Deselect
Power Down Entry
Power Down Exit
and then restarted through the specified initialization sequence before normal operation can continue.
(Extended) Mode Register set Command is issued.
V
REF
must be maintained during Self Refresh operation.
Truth Tables
CKE
Previous
Cycle
H
H
H
H
H
H
H
H
H
H
H
H
L
L
Current
Cycle
H
H
L
H
H
H
H
H
H
H
H
X
X
L
H
CS RAS
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
L
H
L
Chapter 3.5
L
L
L
X
H
L
L
L
H
H
H
H
H
X
X
H
X
H
23
for details.
CAS WE BA0
L
L
L
X
H
H
H
H
L
L
L
L
H
X
X
H
X
H
t
XP
and all read/write bursts must be finished before the
L
H
H
H
L
L
H
L
L
H
H
H
X
X
H
X
H
X
512-Mbit Double-Data-Rate-Two SDRAM
BA1
BA
X
X
X
BA
X
BA
BA
BA
BA
BA
X
X
X
X
A[12:11] A10 A[9:0]
OP Code
X
X
X
X
X
Row Address
Column
Column
Column
Column
X
X
X
X
HYB18T512[40/80/16]0BF
Command Truth Table
X
X
X
L
H
L
H
L
H
X
X
X
X
Internet Data Sheet
X
X
X
X
X
Column
Column
Column
Column
X
X
X
X
TABLE 15
Note
4)5)6)
4)
4)7)
4)7)8)
4)5)
4)5)
4)5)
4)5)9)
4)5)9)
4)5)9)
4)5)9)
4)
4)
4)10)
4)10)
1)2)3)