HYB18T512160BF-2.5 Qimonda, HYB18T512160BF-2.5 Datasheet - Page 42

• Manufacturer Part Number: HYB18T512160BF-2.5
• Description: IC DDR2 SDRAM 512MBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T512160BF-2.5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1016-2

Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
Parameter
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse
width
CK, CK low-level width
Auto-Precharge write recovery +
precharge time
Minimum time clocks remain ON
after CKE asynchronously drops
LOW
DQ and DM input hold time
(differential data strobe)
DQ and DM input hold time (single
ended data strobe)
DQ and DM input pulse width (each
input)
DQS output access time from CK /
CK
DQS input HIGH pulse width (write
cycle)
DQS input LOW pulse width (write
cycle)
DQS-DQ skew (for DQS &
associated DQ signals)
Write command to 1st DQS latching
transition
DQ and DM input setup time
(differential data strobe)
DQ and DM input setup time (single
ended data strobe)
DQS falling edge hold time from CK
(write cycle)
DQS falling edge to CK setup time
(write cycle)
Clock half period
Data-out high-impedance time from
CK / CK
Address and control input hold time
DRAM Component Timing Parameter by Speed Grade - DDR2–533 and DDR2–400
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CCD
CH
CKE
CL
DAL
DELAY
DH.BASE
DH1.BASE
DIPW
DQSCK
DQSH
DQSL
DQSQ
DQSS
DS.BASE
DS1.BASE
DSH
DSS
HP
HZ
IH.BASE
DDR2–533
–500
2
0.45
3
0.45
WR +
t
225
–25
0.35
–450
0.35
0.35
—
– 0.25
100
–25
0.2
0.2
MIN. (
—
375
Min.
IS
+
t
CK
t
t
CL,
RP
+
t
t
IH
CH
42
)
Max.
+500
—
0.55
—
0.55
—
––
––
—
—
+450
—
—
300
+ 0.25
—
—
—
—
t
—
AC.MAX
DDR2–400
–600
2
0.45
3
0.45
WR +
t
275
25
0.35
–500
0.35
0.35
—
– 0.25
150
25
0.2
0.2
MIN. (
—
475
512-Mbit Double-Data-Rate-Two SDRAM
Min.
IS
+
t
CK
t
t
CL,
RP
+
t
t
CH
IH
)
Max.
+600
—
0.55
—
0.55
—
––
––
—
—
+500
—
—
350
+ 0.25
—
—
—
—
t
—
AC.MAX
HYB18T512[40/80/16]0BF
Internet Data Sheet
Unit
ps
t
t
t
t
t
ns
ps
ps
t
ps
t
t
ps
t
ps
ps
t
t
ps
ps
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
TABLE 38
Notes
3)4)5)6)
7)
8)
9)
10)
10)
10)
10)
11)
12)
10)
1)2)