HYB18T512160BF-2.5 Qimonda, HYB18T512160BF-2.5 Datasheet - Page 34

• Manufacturer Part Number: HYB18T512160BF-2.5
• Description: IC DDR2 SDRAM 512MBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T512160BF-2.5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1016-2

1)
2)
3)
4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
5) Definitions for
6) Timing parameter minimum and maximum values for
Detailed
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the
specification. Legend: A = Active; RA = Read with Autoprecharge; D = Deselect.
I
All banks are being interleaved at minimum
inputs are STABLE during DESELECTs. IOUT = 0 mA.
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
Parameter
Self-Refresh Current
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data
bus inputs are floating.
Operating Bank Interleave Read Current
1. All banks interleaving reads,
2. Timing pattern: see
DDR2-400 3-3-3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
DDR2-533 4-4-4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
DDR2-667 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
DDR2-667 4-4-4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
DDR2-800 6-6-6: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D
DDR2-800 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
Parameter
LOW
HIGH
STABLE
FLOATING
SWITCHING
DD7
V
I
I
t
bus inputs are stable during deselects; Data bus is switching.
DD
DD
: Operating Current: All Bank Interleave Read operation
CK(IDD)
DDQ
specifications are tested after the device is properly initialized.
parameter are specified with ODT disabled.
= 1.8 V ± 0.1 V;
I
DD7
,
t
RC
=
I
DD
t
RC(IDD)
Description
Defined as
Defined as
Defined as inputs are stable at a HIGH or LOW level
Defined as inputs are
Defined as: Inputs are changing between high and low every other clock (once per two clocks) for address
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ
signals not including mask or strobes
, see
V
,
Detailed I
DD
Table
t
RRD
= 1.8 V ± 0.1 V.
=
V
V
33.
t
IN
IN
RRD(IDD)
I
≤
≥
OUT
DD7
V
V
IL.AC.MAX
IH.AC.MIN
= 0 mA; BL = 4, CL = CL
timings shown below.
; CKE is HIGH, CS is HIGH between valid commands. Address
V
REF
t
RC.IDD
=
V
DDQ
without violating
I
DD
/ 2
current measurements are defined in Chapter 7.
34
(IDD)
, AL =
t
RRD.IDD
t
RCD(IDD)
using a burst length of 4. Control and address bus
512-Mbit Double-Data-Rate-Two SDRAM
-1 ×
t
CK(IDD)
;
t
CK
HYB18T512[40/80/16]0BF
=
Internet Data Sheet
Symbol
I
I
DD6
DD7
Definition for
TABLE 33
Note
1)2)3)4)5)6)
1)2)3)4)5)6)
I
DD