HYB18T512160BF-2.5 Qimonda, HYB18T512160BF-2.5 Datasheet - Page 38

• Manufacturer Part Number: HYB18T512160BF-2.5
• Description: IC DDR2 SDRAM 512MBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T512160BF-2.5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1016-2

7.2
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
Parameter
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and
low pulse width)
Average clock low pulse width
Auto-Precharge write recovery +
precharge time
Minimum time clocks remain ON after
CKE asynchronously drops LOW
DQ and DM input hold time
DQ and DM input pulse width for each
input
DQS output access time from CK / CK
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew for DQS & associated
DQ signals
DQS latching rising transition to
associated clock edges
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
CK half pulse width
Data-out high-impedance time from
CK / CK
Address and control input hold time
Control & address input pulse width
for each input
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from
CK / CK
MRS command to ODT update delay
Component AC Timing Parameters
DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CCD
CH.AVG
CK.AVG
CKE
CL.AVG
DAL
DELAY
DH.BASE
DIPW
DQSCK
DQSH
DQSL
DQSQ
DQSS
DS.BASE
DSH
DSS
HP
HZ
IH.BASE
IPW
IS.BASE
LZ.DQ
LZ.DQS
MOD
DDR2–800
–400
2
0.48
2500
3
0.48
WR +
t
+
125
0.35
–350
0.35
0.35
—
– 0.25
50
0.2
0.2
Min(
t
—
250
0.6
175
2 x
t
0
Min.
IS
CL.ABS
AC.MIN
t
+
IH
t
AC.MIN
t
t
CH.ABS
CK .AVG
)
t
nRP
38
,
—
—
—
Max.
+400
—
0.52
8000
—
0.52
—
––
––
+350
200
+ 0.25
––
—
—
__
t
—
—
—
t
t
12
AC.MAX
AC.MAX
AC.MAX
DDR2–667
–450
2
0.48
3000
3
0.48
WR +
t
t
175
0.35
–400
0.35
0.35
—
– 0.25
100
0.2
0.2
Min(
t
—
275
0.6
200
2 x
t
0
512-Mbit Double-Data-Rate-Two SDRAM
Min.
IS
CK .AVG
CL.ABS
AC.MIN
+
t
t
AC.MIN
CH.ABS
)
t
nRP
+
t
IH
,
Max.
+450
—
0.52
8000
—
0.52
—
––
––
—
+400
—
—
240
+ 0.25
––
—
—
__
t
—
—
—
t
t
12
AC.MAX
AC.MAX
AC.MAX
HYB18T512[40/80/16]0BF
Internet Data Sheet
Unit
ps
nCK
t
ps
nCK
t
nCK
ns
ps
t
ps
t
t
ps
t
ps
t
t
ps
ps
ps
t
ps
ps
ps
ns
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
TABLE 37
Note
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8)
9)10)
11)
9)10)
12)13)
14)18)19)
8)
15)
16)
17)18)19)
16)
16)
20)
8)21)
22)24)
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8)21)
8)21)
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