HYB18T512160BF-2.5 Qimonda, HYB18T512160BF-2.5 Datasheet - Page 17

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HYB18T512160BF-2.5

Manufacturer Part Number
HYB18T512160BF-2.5
Description
IC DDR2 SDRAM 512MBIT 84TFBGA
Manufacturer
Qimonda
Datasheet

Specifications of HYB18T512160BF-2.5

Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
512M (32Mx16)
Speed
400MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 95°C
Package / Case
84-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
675-1016-2
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing t
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
Field
TM
CL
BT
BL
rounding up to the next integer: WR [cycles] ≥ t
for the analogue t
Bits
7
[6:4]
3
[2:0]
Type
w
w
w
w
WR
timing WR
1)
MIN
Description
Test Mode
0
1
CAS Latency
Note: All other bit combinations are illegal.
011
100
101
110
111
Burst Type
0
1
Burst Length
Note: All other bit combinations are illegal.
010
011
B
B
B
B
is determined by t
B
B
B
B
B
B
B
TM Normal Mode
TM Vendor specific test mode
CL 3
CL 4
CL 5
CL 6
CL 7
BT Sequential
BT Interleaved
BL 4
BL 8
WR
(ns) / t
CK.MAX
CK
(ns). The mode register must be programmed to fulfill the minimum requirement
and WR
17
MAX
is determined by t
512-Mbit Double-Data-Rate-Two SDRAM
CK.MIN
.
HYB18T512[40/80/16]0BF
WR
Internet Data Sheet
(in ns) by t
CK
(in ns) and

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