HYB18T512160BF-2.5 Qimonda, HYB18T512160BF-2.5 Datasheet - Page 37

• Manufacturer Part Number: HYB18T512160BF-2.5
• Description: IC DDR2 SDRAM 512MBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T512160BF-2.5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1016-2

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Period
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
input reference level is the crosspoint when in differential strobe mode.
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
@ CL = 3
@ CL = 4
@ CL = 5
Symbol Min.
t
t
t
t
t
t
t
CK
CK
CK
RAS
RC
RCD
RP
V
–3
4–4–4
5
3
3
45
57
12
12
DDR2–667C
REF
V
stabilizes. During the period before
TT
.
Max.
8
8
8
70k
—
—
—
DDR2–667D
–3S
5–5–5
Min.
5
3.75
3
45
60
15
15
37
Max.
8
8
8
70k
—
—
—
DDR2–533C
–3.7
4–4–4
Min.
5
3.75
3.75
45
60
15
15
V
REF
512-Mbit Double-Data-Rate-Two SDRAM
stabilizes, CKE = 0.2 x
Max.
8
8
8
70k
—
—
—
DDR2–400B
–5
3–3–3
Min.
5
5
5
40
55
15
15
HYB18T512[40/80/16]0BF
Speed Grade Definition
Max.
8
8
8
70k
—
—
—
V
DDQ
Internet Data Sheet
Unit
t
—
ns
ns
ns
ns
ns
ns
ns
TABLE 36
CK
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
t
REFI
.