HYB18T512160BF-2.5 Qimonda, HYB18T512160BF-2.5 Datasheet - Page 3

• Manufacturer Part Number: HYB18T512160BF-2.5
• Description: IC DDR2 SDRAM 512MBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T512160BF-2.5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1016-2

1
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main
characteristics.
1.1
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
• 1.8 V
• DRAM organizations with 4,8,16 data in/outputs
• Double Data Rate architecture: two data transfers per
• Programmable CAS Latency: 3, 4, 5 and 6
• Programmable Burst Length: 4 and 8
• Differential clock inputs (CK and CK)
• Bi-directional, differential data strobes (DQS and DQS) are
• DLL aligns DQ and DQS transitions with clock
• DQS can be disabled for single-ended data strobe
• Commands entered on each positive clock edge, data and
• Data masks (DM) for write data
• Posted CAS by programmable additive latency for better
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
1.8 V
clock cycle four internal banks for concurrent operation
transmitted / received with data. Edge aligned with read
data and center-aligned with write data.
operation
data mask are referenced to both edges of DQS
command and data bus efficiency
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
±
±
0.1 V Power Supply
0.1 V (SSTL_18) compatible I/O
Overview
Features
3
• Off-Chip-Driver impedance adjustment (OCD) and
• Auto-Precharge operation for read and write bursts
• Auto-Refresh, Self-Refresh and power saving Power-
• Average Refresh Period 7.8 µs at a
• Programmable self refresh rate via EMRS2 setting
• Programmable partial array refresh via EMRS2 settings
• DCC enabling via EMRS2 setting
• Full and reduced Strength Data-Output Drivers
• 1KB page size for ×4 and ×8, 2KB page size for ×16
• Packages: PG-TFBGA-60, PG-TFBGA-84
• RoHS Compliant Products
• All Speed grades faster than DDR2–400 comply with
On-Die-Termination (ODT) for better signal quality
Down modes
than 85 °C, 3.9 µs between 85 °C and 95 °C
DDR2–400 timing specifications when run at a clock rate
of 200 MHz.
512-Mbit Double-Data-Rate-Two SDRAM
1)
HYB18T512[40/80/16]0BF
Internet Data Sheet
T
CASE
lower